DiaVision Professional V4.0

Professional Edition
DiaVision™ Professional Edition includes all the features of DiaVision™ Standard Edition listed above plus the following unique features:

Recut - DiaVision™ can tell you how and what to do if you want to improve the diamond cut (diamond proportions and symmetry). Works on round and fancy diamond shapes.
Real three-dimensional model - view your diamond like never before! The real three-dimensional model shows you each extra diamond facet, misshapen facet, misaligned facet junction, broken culet, and all other symmetry features of your diamond in a clear and unmistakable way.
Three-dimensional model rotation - freely rotate your diamond's three-dimensional model in any way you like, so you can zoom in to any stone feature you're interested in.
New Shape Wizard - "teach" DiaVision™ how to accurately measure new, proprietary diamond shapes, so you can regularly measure them with DiaVision™ and print out the reports and labels you're used to.
Export shape to DiaExpert™ - this feature is a must for diamond manufacturers who want to create new diamond shapes. Simply scan your new diamond shape with DiaVision™ and with a click of a button export that shape into DiaExpert™, for planning rough diamonds with your new diamond shape.




Product Options & Extensions
DiaVision™ has three options that may be configured and customized to suit your specific needs:

Search & Find - Use DiaVision™’s Search & Find feature to positively identify your diamonds:

As a wholesaler: Positively identify your stones – when sending out stones on memo, you may want to positively identify them upon their return. Simply use the new “Search & Find” feature and instantly verify that your stones haven’t been switched.
As a retailer: Upgrade stones – when a client comes in with a stone he bought from you a year ago and now wants to upgrade, you can instantly verify that he’s indeed returning the same stone he bough, and not a substitute.
As a manufacturer: Match pairs and sets– when creating jewelry pieces that require a pair or a set of near-identical stones, DiaVision™’s “Search & Find” feature will search through your stock and find stones as similar as you like to the one you just scanned.
As a gem lab: Report resubmitted stones – as a gemological laboratory, you may have stones resubmitted from time to time. It could be very valuable to you if DiaVision™ immediately alerted you to the fact that this stone was scanned by your Sarin. machine in the past. You can then load the previous report you issued on that stone and avoid embarrassing discrepancies and mistakes.

GT-STRUDL-V29.1

STRUCTURAL DESIGN & ANALYSIS SOFTWARE

GT STRUDL is one of the most widely used Structural Design & Analysis software programs for Architectural - Engineering - Construction (AEC), CAE/CAD, utilities, offshore, industrial, nuclear and civil works. GT STRUDL is a fully integrated general-purpose structural information processing system capable of supplying an engineer with accurate and complete technical data for design decision making.
GT STRUDL completely integrates graphical modeling and result display, frame and finite static, dynamic, and nonlinear analysis, finite element analysis, structural frame design, graphical result display, and structural database management into a powerful menu driven information processing system. In over 30 years of use, GT STRUDL is one of the most widely accepted computer-aided engineering and design tools for the structural analyst and structural design engineer. GT STRUDL is used on a regular basis by thousands of engineers in over 30 countries.
GT STRUDL is a world class computer-aided structural engineering software system for assisting engineers in the structural analysis and design process. It is a sophisticated, efficient, highly reliable, and fully integrated general purpose structural information processing system capable of supplying an engineer with accurate and complete technical data for design decision making.
GT STRUDL completely integrates graphical modeling, frame and finite static, dynamic, and nonlinear analysis, finite element analysis, structural frame design, graphical result display, and structural database management into a powerful menu-driven information processing system. In over 30 years of use, GT STRUDL is one of the most widely accepted Computer-Aided Engineering and Design (CAE/ CAD) tools for the structural analyst and structural design engineer. GT STRUDL is used on a regular basis by thousands of engineers in over 30 countries.

The GTSES sparse equation solver, first implemented under the STIFFNESS ANALYSIS GTSES command in Version 29, has been implemented as a stand-alone program. When executed as such, the GTSES sparse equation solver is able to allocate all available virtual memory to its own execution process, thereby increasing the efficiency of the equation solution beyond the improvements already made by the STIFFNESS ANALYSIS GTSES command.

The STIFFNESS ANALYSIS GTSES command also stores the results of the analysis (joint displacements, member and finite element forces, finite element stresses and strains, reactions and resultant joint loads) in files in the current working directory, further increasing the size of static analysis models that can be solved and the efficiency with which they are solved.

• An example of a large model execution which completed in Version 29.1 but ran out of memory in Version 29 is shown below:

Number of Joints
40042
Number of Members
3055
Number of Elements
41332
Number of Loadings
50
Number of Loading Combinations
48
Average Bandwidth + Standard Deviation
584

Time to solve using GTSES for 240,252 degrees of freedom = 197 seconds

Total STIFFNESS ANALYSIS GTSES time = 767 seconds

• The AREA LOAD command has improved geometrical error detection and reporting. In addition, the total area and applied load are now printed as an additional verification tool.

• The output from the DESIGN SLAB command was modified to display a full listing of elements selected and used in the computation of the total moment acting on a cut section, for both the Wood & Armer and element force algorithms. The DESIGN SLAB command remains a prerelease feature in Version 29.1.

Metalix-cnkcad-v8.5

The cncKad software system offers the full range of CAD/CAM capabilities for use with CNC Punch, Laser, Plasma and Flame machines. cncKad supports the entire cycle of CNC operations and includes drafting, automatic and interactive processing modes, post processing, graphic simulation of CNC programs, manual or automatic nesting, downloading and uploading of NC files.

Advanced CAD/ CAM solution for the Sheet Metal manufacturer
Supports the entire design to production cycle
Jobs can be ported to different machines or technology with a few clicks of the mouse
Variety of Punch, Laser, Plasma and Flame machines supported
optimal material utilization with Auto Nest best fit nesting solution
Advanced technology combines drafting and processing in the same module
Create efficient CNC programs with precision and ease
Import and export of DXF, IGES, CADL, DWG and other standard file formats.

2008 January 0day sofrware

2008-01-31 Teksoft.CamWorks.v2008-08.SP0.1
2008-01-31 Nemetschek_Allplan_BIM_v2008_MULTiLANGUAGE
2008-01-30 FORMZ.RENDERZONE.PLUS.V6.5.4
2008-01-30 DELCAM_EXCHANGE_V5.3.0105
2008-01-29 MSC.SimManager.Enterprise.R3
2008-01-28 Dassault.Systemes.CATIA.P2.v5R18.SP3.MULTiLANGUAGE.DVD.forWIN32&WIN64
2008-01-28 CSC.TEDDS.V10
2008-01-28 ATIR.STRAP.AND.BEAMD.V12.5
2008-01-27 CSC.FASTRAK.V14
2008-01-26 MSC.MD.Nastran.R2.1
2008-01-26 Baramundi.Management.Suite.v7.5.3.BiLiNGUAL
2008-01-26 Simatic.Step7.Professional.Edition.2006.SR4.MULTiLANGUAGE
2008-01-25 UGS.NX.I-DEAS.5M1
2008-01-24 Cigraph.ArchiMaterial.v1.0.For.Archicad.11.Multilangual
2008-01-24 Cigraph.ArchiQuant.v1.0.For.Archicad.11.Multilangual
2008-01-23 Simulia.Abaqus.v6.7.EF.Linux.32bit.Crackfix
2008-01-20 AUTODESK_COMBUSTION_V2008
2008-01-20 SPSS_v16.0.1_GERMAN
2008-01-20 Cimmetry.AutoVue.Electro-Mechanical.Pro.v19.2c2.WIN32
2008-01-20 Cimmetry.AutoVue.3D.Web.Edition.v19.2c2.WiNNT2K-
2008-01-18 SIEMENS_NX_NASTRAN_X86.X64_V5.1
2008-01-18 DELCAM_DUCTPOST_V1.4.90
2008-01-17 DELCAM_POWERMILL_V8_CB1098025_SP4
2008-01-16 Bentley.WaterCAD.XM.v08.09.400.3
2008-01-16 Bentley.WaterGEMS.XM.v08.09.400.34
2008-01-16 Premier.v12.2.621.iSO.Multilanguage
2008-01-15 Simulia.Abaqus.v6.7.EF.32bit
2008-01-13 California_3000_v8.2.03_GERMAN
2008-01-12 SPECTRUM.MICROCAP.V7.08
2008-01-12 Cadenas.Partsolutions.v8.1.05.Multilanguage
2008-01-11 UGS.Solid.Edge.v20.0.GERMAN
2008-01-10 MSC.SIMOFFICE.R2.2
2008-01-10 Bentley.speedikon.Project.Editor.v08.09.00.31
2008-01-09 SPSS.DIMENSIONS.MRSTUDIO.V4.5
2008-01-09 SPSS.Dimensions.Desktop.Author.v4.5
2008-01-09 SPSS.Dimensions.mrTranslate.v4.5
2008-01-09 SPSS.Dimensions.mrPaper.and.mrScan.v4.5
2008-01-08 CIVIL_DESIGNER_V6.4_R12
2008-01-08 ALLYCAD_V3.5_R12
2008-01-07 Bentley.CADScript.v08.09.04.09.for.Microstation.XM
2008-01-07 Bentley.speedikon.Architectural.v08.09.00.31.for.Powerdraft.XM
2008-01-06 VectorWorks_v2008_SP1_GERMAN
2008-01-06 Hampson.Russell.CE.v8.R2.WIN32&Win64
2008-01-06 ADAPT_BUILDER_EX_V3.2
2008-01-06 ADAPT_PT_V8.003
2008-01-06 DP.TECHNOLOGY.ESPRIT.V2008
2008-01-06 BIO-RAD_QUANTITY_ONE_V22
2008-01-06 BIO-RAD_PDQUEST_V8.0.1
2008-01-06 POINTWISE_GRIDGEN_V15.11_READ_NFO
2008-01-04 Cimatron Elite V8.5
2008-01-03 Bentley.PowerMap.XM.v08.09.04.32
2008-01-03 Bentley.speedikon.Architectural.v08.09.00.31.for.MicroStation.XM
2008-01-03 Bentley.speedikon.Industrial.v08.09.00.31.for.MicroStation.XM
2008-01-01 Comsol.v3.4.DVD.MULTiLANGUAGE
2008-01-01 Excellink_for_AutoCAD_2008_v18.0.1.70917_Incl_Keygen
caxsoft

Mentor-Graphics-Expedition-Enterprise-Flow-v2007

Expedition Enterprise provides a complete solution for PCB and FPGA design, embedded in a global enterprise environment. Component selection in a centralized and configurable data management system permits part selection based on electrical characteristics and business criteria (e.g., product line, vendor, RoHS criteria, cost). The data are updated through process integration with PLM or MRP systems. Filters can be set to restrict use of component categories
Mentor Graphics Corp. has announced its new Expedition Enterprise flow for PCB systems design. This flow enables large electronics companies to leverage their multi-disciplined design team resources, and create and provide access to their intellectual property on a global basis. It also allows companies to integrate their design data with corporate PLM, and supply chain and manufacturing systems, as well as to communicate with outsourced design and manufacturing. Expedition Enterprise can improve competitiveness and performance by combining advanced PCB design technology with library and design data management, and a unified constraint editing system.

Expedition Enterprise addresses the challenges of the global enterprise, including intellectual property management, supply chain integration, and design team management across multiple sites. It integrates and manages the system design flow and enables seamless data transfer among design teams, improving designer productivity and design team collaboration, while facilitating communication with the corporate enterprise. This new solution offers improved library management which simplifies supply chain management, increases library quality, and reduces product costs. Expedition Enterprise also integrates FPGA and PCB design flows, allowing concurrent design that leverages the FPGA's I/O flexibility, and addresses routing and timing challenges, and facilitates common design constraint management. Expedition Enterprise is available on multiple hardware platforms to support existing hardware investments

"Expedition Enterprise is the culmination of recent technology acquisitions combined with significant engineering effort to deliver the next-generation PCB systems design solution," stated Henry Potts, vice president and general manager of Mentor Graphics' Systems Design Division.

Key Capabilities:
>Library creation. Creates all library elements in a single design environment, leveraging the supply chain for web-based components that minimize library development time and increase its quality
Design data management. Manages library and design data to ensure appropriate access to and integration with corporate product life-cycle management systems
Constraint editor system. Provides common rule definition and verification environment for physical and electrical constraints, from design capture through layout
Design definition. Utilizes powerful hierarchy to capture large designs quickly, reuse proven circuits and attributes, and manage hundreds of variant designs
Functional verification. Quickly simulates analog, digital and mixed-signal circuits within an integrated environment
PCB/FPGA co-design. Concurrently designs an integrated FPGA/PCB system for optimal system performance and reduced design cycle time
Signal integrity verification. Leverages an advanced multi-lingual device and interconnect modeling environment to verify the integrity of synchronous and asynchronous signals
Design layout. Utilizes AutoActive correct-by-construction methodology to place and route complex PCBs in a single design environment based on constraints for advanced interconnect and high-speed
Concurrent team layout. Optimizes design team resources and reduces design cycle time through simultaneous design on a common database
Design for fabrication. Runs fabrication checks and facilitates fixes in a single environment, reducing design cycle iterations and increasing design manufacturability
Manufacturing preparation. Easily creates and validates board panels, copper balancing, and product documentation within the common layout editor
Process customization. Automates and extends the design environment using industry-standard languages to achieve company-specific design process optimization

Shoemaster-QS-V7.1

Shoemaster Power includes all of the functionality of Esprite and Classic and offers even more powerful features by supporting a 3D shoe last as well as the 2D standard.

Shoe styles can be created and viewed in 3D on the last. The comprehensive Last Flattening System then provides a seamless and efficient transition from the last to pattern engineering.


In addition to the standard flattening tools, Shoemaster Power now includes the Expert Flattening System which uses wizards and databases of rules and measures to guide shoemakers through the most difficult and technical operations.

Shoemaster Power has been specially developed to meet modern shoemaking needs. It includes full 3D grading features and allows computerised e-Lasts to be downloaded from last making companies in a matter of seconds.

Its 3D functionality allows you to encompass more of your existing process in a virtual environment. This reduces the costs associated with rework, as well as maximising the productivity of your last making, pattern engineering and grading departments. Shoemaster Power includes highly flexible 3D last modelling tools, 2D and 3D pattern and styling tools and a Grading Interface that is respected throughout the industry
Beginning with a last and a simple sketch, you can rapidly design the complete shoe in 3D with any combination of colours, textures, units and components. The result is a completely realistic 3D visualisation that is ideal for presentations to buyers and manufacturers.


Shoemaster Creative contains all the functionality necessary to produce attractive and convincing shoe designs. E-Lasts can be imported directly in digital form and, where necessary, modified by the program to meet the design concept. 2D sketches can also be imported as scans, and the program can interface directly with conventional graphics packages like Adobe PhotoShop. The 2D design can then be traced directly onto the last, and then units, colours and textures added to create a true 3D version of the design. Finally, buckles and other components can be imported and positioned to produce a complete 3D visualisation of the shoe.

Shoemaster Creative provides a genuine opportunity to streamline production and cut costs by significantly reducing the need for the manufacturing of shoe samples. It also integrates fully with the Shoemaster 3D pattern engineering systems, so any effects of the pattern engineering process can be seen immediately in the shoe design

AGILENT.IC-CAP.V2006B

IC-CAP (Integrated Circuit Characterization and Analysis Program) is a device modeling program that provides powerful characterization and analysis capabilities for all of today's semiconductor modeling processes.

IC-CAP offers device engineers and circuit designers state-of-the-art modeling software that performs numerous modeling needs including instrument control, data acquisition, graphical analysis, simulation, optimization, and statistical analysis.

All of these processes are combined into a flexible and intuitive software environment for efficient and accurate extraction of active device and circuit model parameters. IC-CAP also provides the power to build model libraries for Agilent EEsof EDA and other simulators.

Add-on 3 includes the following extra content:

BSIM3, BSIM4 and PSP Modeling Packages Enhancements
All the MOS Extraction Packages feature a new data architecture that makes it easier to import measured data generated by other measurement software solutions into IC-CAP for model extraction. Previous limitations about data have been removed and users can now associate customized sets of measurements to different devices. Adaptive gate voltage measurements based on threshold voltage are now supported. In addition, new functionalities were added to the extraction modules to make the flow more efficient, easier to use and more customizable.

IC-CAP Platform Enhancements
New features include a faster link to Synopsys' HSPICE on Solaris and LINUX platforms and - thanks to a new IC-CAP input type called LSYNC - simulation of MOS devices with different parameters such as L and W in a single setup are now extremely efficient.

A new UI tool called Model Organizer lets users conveniently re-organize the IC-CAP model tree structure: setups, transforms, plots, etc.

Several new PEL functions have been added and a convenient example directory called "New_Features" includes example model files designed to provide quick start guides and examples on how to use the new features.

IMPORTANT NOTE. Add-on 3 will only support HSPICE versions 2006.09 and higher. Therefore, if you are using an earlier version of HSPICE you should not install Add-On 3.

top of page

IC-CAP 2006: Smarter + Flexible + Efficient = Better extraction flow!
The IC-CAP 2006 release is one of the biggest advances to the IC-CAP platform with new performance and features.

The IC-CAP 2006 release introduces a new graphical and plotting utility, MultiPlot Studio. It offers the ability to improve your modeling efficiency and accuracy by visualizing the details of your extraction flow.
The new BSIM4 Toolkit will allow you to see reductions in your modeling extraction process by as much as 50%.
The first introduction of IC-CAP on a Linux platform.
Click on the following link for complete release details:

IC-CAP 2006 - What's New
Platform Support
The following operating systems are supported in IC-CAP 2006:

PC: MS Windows 2000 / XP
Red Hat Enterprise WS 3.x Linux
UNIX: HP-UX 11i, SUNOS 8, 9, 10.

RM2006 (c) TDV

Modelling of 3D structures using a CAD like pre-processor including definition of project axis in plan and elevation.
The 3D structure is analysed allowing the simulation of any erection procedure linking the erection with to the time axis in the calculation (4D).
There are no limitations regarding bridge type and erection sequence.
14 international design code are currently incorporated and the program carries out specific SLS and ULS design code checks in accordance with these standards.
The program is in use by many international consultants and a few thousand bridges worldwide have been designed using this powerful engineering tool.

The following practical applications are specifically supported by the program:
Classical composite structure
Steel girder and concrete slab - the "classical" composite structure problem.
Different types
Different types of concrete (quality or age) combined in one single cross section, e.g. pre-cast (pre-stressed) beam and cast-in-place-slab.
Additional module
The following functions are available in this additional module:
Cross sectional characteristics
Integration of the individual parts of the total composite section. The cross sectional characteristics of the composite section are computed automatically by using the given values of the individual parts and taking their relative geometric positions into account.
The results are related either to the individual section parts, or to the integrated composite section, depending on the situation in the different calculation processes.
In every case the program will derive the individual results for each section part and will decompose the value for the composite section into the individual parts. All post processing functions (design code checks, graphics, etc.) can therefore be performed for the individual section parts as well as for the composite sections.
Pre-stressing, creep and shrinkage
Each part of this cross section can be individually identified for pre-stressing, creep and shrinkage. The user specifies the appropriate coefficients according to the individual age of concrete and the time step.
The calculation of time dependent displacements and internal forces - for individual parts as well as for composite sections - is carried out by using the same algorithm as described in the pre-stressed concrete structures technical description.
Construction stages
Generally the same features for construction stages are available as those described in the pre-stressed concrete structures technical description. An additional feature in this module makes it possible to activate an individual part of the composite section in a single construction stage. This allows not only the changing of the structural system, but also of the cross section during the construction stage sequence.
Each part of the section may be individually pre-tensioned or post-tensioned. All pre-tensioning and post-tensioning functions can be used and are described in detail in the technical description for "pre-stressed concrete analysis".
Shear connectors
As a unique a feature RM2006 contains a specific element type allowing the design of this structural part as well. The shear connector element is activated automatically when a composite cross section is completed. All results (loading cases as well as envelopes from superposition files) are available for these elements as well (only normal force is of interest!)

Mentor-Graphics-Calibre-v2007 (c)Mentor.Graphics

Allows large designs to be opened rapidly
Supports automatic chip finishing operations through a TCL programming API
Allow users to cut, copy, paste, delete, move and more with unlimited undo/redo function; and access native data within the GDSII database, including polygons, edges, text, cells, instances, arrays and more.
Fast, streamlined iteration loop through integration with Calibre Interactive and RVE
Quick GDSII loading, viewing, error identification, modification and re-invocation

Benefits:
Dramatically reduces time to tape-out
Allows convenient re-verification of the full design, or only the data that has been modified
Efficiently automates chip finishing tasks
Calibre RVE
Allows cross probing of results between layout, schematic, source netlist, layout netlist and LVS result files
Enables viewing of all parasitics in the Parasitic Browsing window
Highlights to schematic capture tools
Automated short isolation debugging
Fast and intuitive hierarchical SPICE browser for source and layout netlists

Benefits

Seamless integration with popular design environments preserves the investment in EDA tools
Quick, intuitive debugging in cell/block and full-chip designs
Calibre YieldAnalyzer
Determines location of the most significant yield improvement opportunities and provides graded yield metrics by issue, cell, window, etc.
Assesses the weighted "grayscale" of features that fail to meet recommended rules.
Assesses the weighted sensitivity to random particles using critical area analysis.
Runs analysis directly on GDSII, OASIS, MilkyWay, and OpenAccess design databases.
Benefits:
Provides manufacturing teams a method of communicating yield and yield modeling information to the design teams.
Executes and visualizes analysis from within all the popular layout environments, including Mentor Graphics IC Station and Calibre DESIGNrev, Cadence® Virtuoso/Encounter, Synopsys® Astro and Magma BlastFusion.
Helps designers see through the fog of DFM rule violations, enabling the ability to make decisions and trade-offs about yield impact issues.

Cimatron E v8.5

The Master Solution is the most comprehensive, integrated CAD/CAM solution for toolmakers. Incorporating Cimatron’s best-of-breed applications for design, modeling, electrodes and NC, CimatronE covers the full toolmaking process.
Powerful modules for a broad range of capabilities are integrated in a single package, bringing you the highest quality with new speed and flexibility. Powerful NC capabilities, from simple 2.5-axis to continuous 5-axis, cover the entire machining process, with polish-less surface quality, high milling efficiency and ease of use. CimatronE boosts efficiency and eliminates common design bottlenecks, resulting in increased productivity for the entire design and manufacturing process.
With CimatronE, your business benefits from tighter control, better responsiveness to change, quicker delivery and lower overhead.

| Product Highlights
Integrated solution – from quoting to delivery
Best-of-breed applications, including Parting, Mold Design, Electrode and NC
Best and most flexible hybrid solid/surfacing modeling system available
Full associativity across the entire toolmaking process – control change, reduce human error and improve productivity
No data exchange required between CAD, CAM and Electrode processes
Designed for concurrent engineering
Automated applications combined with full user control
Extremely flexible – engineering resources can be moved between tasks and stages along the process
Single CAD/CAM environment, single CAD/CAM provider
[Back to Top]
| Key Benefits
Faster delivery time
Increased productivity
Ease of use
Handles any tooling job, on any part, solid or surfacing
Built-in change management
Expert implementation and customization
World-class customer support
[Back to Top]
| Features
Quoting
Data Translation
ECO management
Preliminary Design
Parting
Tool Design
Purchasing
Drawing
Electrode design & manufacture
EDM set-up
NC Programming, 2.5- to 5-axis
Shop floor – NC Lite

ESI CFDRC-V2008

CFDRC has a growing inventory of Patents, Prototypes, and Software, which provide head start for many customer solutions.

Patents Portfolio
Biomedical Devices
Combustion Devices
Propulsion Devices
CFD & Multiphysics Software
Multiscale, Multifidelity Software
Custom Software
Partnering for Success
Credible and Reliable Business Partner for:

Engineering Product Development
Intellectual Property Development
Multi-scale, Multi-Physics Simulations
Customized Software Development
Strategic Business Collaborations
R&D Collaboration (Software and Hardware)
Prime Contractor / System Integrator Support
Simulation based Safety, Reliability & Certification Analysis and Design Support


Leverage CFDRC Capabilities:

New Technologies Developed with over $10M/Year R&D Funding
Expertise in Technology Application and IP generation
Steady Profitable Growth Since Inception in 1987
Winner of First National "Tibbetts Award", and a second Tibbetts Award in 2006. Rated in top 10% of Small Businesses Nationwide for Commercialization of Innovative Research and Technology
Woman owned small business
Quality & Reliability

CFDRC has well-developed procedures for:

Efficient execution of projects, under CPFF, T&M, and FFP contracts
Full protection of sensitive data (including Proprietary, ITAR and Classified information)
Exclusive and Non-exclusive licenses of technology
Generation of Intellectual Property (Patents)
Protection of IP and potential infringements

2007 December 0day sofrware release

2007-12-31 MasterCAM_X2_MR1_v11.1_GERMAN
2007-12-30 DATAM.COPRA.RF.V2005.SR1
2007-12-30 AUTODESK.P.AND.ID.V2008
2007-12-30 AUTODESK.LAND.DESKTOP.V2008.SP2
2007-12-30 AUTODESK.CIVIL.3D.LAND.DESKTOP.COMPANION.V2008.SP2
2007-12-30 SPSS.V16.0.LINUX &Win
2007-12-29 Abaqus.for.CATIA.v2.5.2.for.CATIA.v5R18
2007-12-29 INVENSYS.SIMSCI.DYNSIM.V4.2.4
2007-12-27 PTC.PRO.ENGINEER.WILDFIRE.v3.0.M120.WIN32&WIN64
2007-12-25 TEKLA.STRUCTURES.V13.1
2007-12-24 LMS.Imagine.Lab.AMESim.v7.0a
2007-12-24 Think3.ThinkiD.DesignXpressions.v2007.1.49.GERMAN
2007-12-24 Autodesk_3ds_Max_2008_GERMAN
2007-12-23 Siemens.Plant.Simulation.v8.1.MULTiLANGUAGE
2007-12-22 ESRI.ArcPad.v7.1
2007-12-21 GibbsCAM.2007.v8.7.9
2007-12-20 BENTLEY_STAAD_PRO_V2007.2
2007-12-20 BENTLEY_STAAD_FOUNDATION_V4.0
2007-12-19 MSC.SimDesigner.R2.for.CATIA.V5.R17
2007-12-19 CSI_SAP2000_V11.0.8
2007-12-19 Autodesk.Mental.Ray.Standalone.v3.6.1a
2007-12-18 SIEMENS.NX.NASTRAN.V5.1
2007-12-17 ISIGHT-FD.v2.5.5
2007-12-17 CA.AllFusion.Model.Manager.v7.2
2007-12-17 Simufact.Forming.v8.0.SP2.Win32.BiLiNGUAL
2007-12-17 Siemens.Plant.Simulation.v8.1.WiNNT2K
2007-12-16 ALGOR.FEA.v21.WiNNT2K
2007-12-16 Innovmetric_PolyWorks_v10
2007-12-15 AUTOFORM.MASTER.V4.1.1
2007-12-14 INSCRIBER_VMP_V4.7_SP8
2007-12-12 BRAINSTORM_ESTUDIO_V11
2007-12-10 DELCAM.ARTCAM.PRO.V2008
2007-12-09 Nihon.Unisys.Dynavista.v7.7.WiNNT2K &win64
2007-12-09 IronCAD.v10.0.WiNNT2K
2007-12-09 GibbsCAM.2007.v8.7.7
2007-12-08 OPENMIND.HYPERMILL.V9.6
2007-12-07 THINK3.THINKDESIGN.THINKID.V2007.1.49
2007-12-06 SIEMENS_NX5.0.2.2_UPDATE
2007-12-06 Bentley.MAPscript.XM.v08.09.04.04
2007-12-06 SOLIDWORKS.V2008.SP1.X86.UPDATE
2007-12-06 IMSI.Turbo.FLOORPLAN.Home.and.Landscape.Pro.v12
2007-12-05 IMSI.Turbo.FLOORPLAN.Landscape.and.Deck.v12.ISO
2007-12-04 CD-adapco.Star-CCM.Plus.and.Cad.Series.v2.10.Windows&Linux
2007-12-03 Vero_VISI_Series_v15.0_MULTiLANGUAGE
2007-12-03 IMSI.TurboCAD.Professional.v14.incl.Symbol.Packs.ISO
2007-12-03 NI.LabVIEW.with.Embedded.Support.v8.5.DVD
2007-12-03 NI.LabWindows.CVI.FDS.v8.5.ISO
2007-12-01 DASYLab.v10.0.BiLiNGUAL.ISO
from caxsoft

Mentor-Graphics-FPGA-Advantage V7.3

FPGA Advantage is a complete Integrated Design Environment (IDE)
targeting high-complexity FPGA device design. The FPGA Advantage IDE
spans the RTL FPGA design flow featuring advanced design entry,
verification, synthesis and implementation sub-flows. FPGA Advantage
accelerates total product design with integration of FPGA IO design
as well as bi-directional integration of the PCB design flow. This
latest release extends the FPGA Advantage IDE to include:
- Improved integration with Precision Synthesis
- Increased "ease of use"
- Extended synthesis device support

Language Independence.
The only unified flow that lets you design for

Any Silicon:
PLD, FPGA, Platform FPGA, Structured ASIC, ASIC Prototypes, ASICs and SOCs
Any Vendor:
Actel, Altera, Atmel, ChipExpress, Lattice, Xilinx, plus any ASIC foundry
Any Language:
VHDL, Verilog, SystemVerilog, C/C++, PSL, SVA

Delivering the technical edge

Maximize QoR, Fmax and area utilization on every leading FPGA platform
Optimize FPGA timing closure with Precision Synthesis and advanced timing analysis
Optimize system timing closure with I/O optimization & PCB integration
Fastest, standards based, multi-lingual simulation platform available

Optimizing your design process

Cut design time in half: Rapid design development process
Practical reuse: RTL reuse methodology
Team productivity: Team design flow and version management
Tune your competitive edge: Flow management and customization
Cut lab time with: FPGA-centric analysis and debug

Optisystem-V6.0

The latest version of OptiSystem features a number of requested enhancements to address the design of passive optic network (PON) based FTTx, optical wireless communication (OWC), and radio over fiber systems (ROF).

Comprehensive Multimode Library

The Multimode Component Library of OptiSystem 6.0 includes an exciting new feature empowering users with the option to load multimode fibers measurements of modal delays and power-coupling coefficients using the Cambridge file format. As result, users now can calculate the MMF link frequency responses faster allowing extensive statistical modeling of multimode-fiber links.

Sophisticated Amplifier Library

Design a variety of waveguide and fiber optic amplifiers using OptiSystem. Determine the tradeoffs between EDFAs, EYDFs, EYDWs, YDFs, SOAs and Raman amplifiers cost and performance. OptiSystem 6.0 automates the analysis of laser pulses by plotting autocorrelation and FROG (Frequency Resolved Optical Gating) graphs directly from the optical time domain analyzer.

New Component Libraries

Bidirectional Optical Fibers: A new discretization parameter for broadband sampled signals offers improved performance, accuracy, and convergence for doped amplifier gain and Brillouin calculations.

Wideband Traveling Wave SOA: Flexible selection between a static or dynamic model.

AWG NxN Bidirectional: A sophisticated new AWG model facilitates the design of AWG based PON using the unique bidirectional capabilities of OptiSystem.

Optical Sources: VCSEL Laser and Laser Rate Equations: A new adaptive step engine allows for fast convergence of high frequency analog signals.

CATV Carrier Generators: New parameters include the ability to enable or disable specific channels, facilitating the measurements of carrier to noise ratio (CNR).

Carrier Generator Measured: A new list of pre-defined set of standard carrier spacing allows for easy setting up of PAL GB (up to 97 channels), NTSC (up to 157 channels) and L (up to 58 channels) systems.



Microwave components

180 and 90 Degree Hybrid Couplers, DC blockers, power splitters and combiners: A new component library geared for ROF applications. Applications include mixers, power combiners, dividers, modulators, and phased array radar antenna systems. Control amplitude and phase balance of different components.

Measured components: Bidirectional S-parameters components allow users to load s1p, s2p, s3p and s4p file formats, including s2p with noise figure data.

Passives

Polarization Delay and Phase Shift components: New components which control the delay and phase shift for each polarization. Control the delay calculation, by using linear or discrete delay.

Periodic Optical Filter: A new multi-band optical filter with user defined transmission function.

Regenerators

MLSE (maximum likelihood sequence estimate) Electronic Equalizer: Introducing an advanced component feature using the Viterbi algorithm to equalize the input signal through a dispersive channel.

Free Space Optics

OWC (Optical Wireless Communication) Channel: A subsystem of two telescopes and the optical wireless channel between them facilitating the simulation of intersatellite communication links. FSO is a telecommunication technology that uses light propagating in free space to transmit data between two points. The technology is useful where the physical connection of the transmit and receive locations is difficult, for example in cities where the laying of fiber optic cables is expensive.

Laker-v3.2-v1p5 (c)Silicon Canvas

Major Benefits

Cuts layout time in half while sustaining important aspects of handcrafted layout density
Total system allows user to create layout from floor planning, device creation, placement, wire connection, to layout verification and correction without the need for data translation
Supports latest process design rules to meet the physical implementation requirements of Ultra-Deep-Submicron (UDSM) and Design-For-Manufacturing (DFM)
Fully customizable bind keys to increase individual productivity and reduce the learning curve for new users
Device-level manipulation reduces tedious/error-prone layout creation and editing.
Shape and Grid Based routers for both full custom and cell-based design applications
Download foundry-certified Laker technology files to instantly use the plug-and-play Laker solution
Schematic-Driven Layout Flow works efficiently with legacy and new designs



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Major Features

Integration Capability
Versatile System:
Import designs from EDIF, Spice netlist, or work with Laker-AMS to perform Schematic-Driven Layout flow.
Integration with 3rd party physical verification solutions:
Tight link with Mentor Graphics Calibre and Synopsys Hercules for DRC/LVS. Run Calibre or Hercules on one block or the whole chip directly from the Laker menu.

Layout Planning
Custom Floor Planner:
Supports block area estimation with reshaped aspect ratio. Assigns pin locations automatically and
provides congestion map information to offer best-practice floor planning scheme. Mixes Soft and Hard Instances to minimize the gap between top-down planning and bottom-up layout realization.
Stick Diagram Compiler:
Provides a higher level of abstraction enabling more efficient transistor floorplanning, such as gate
merging, swapping and splitting.
Automatic Transistor Placer:
Optimum transistor placement achieved automatically through chaining, folding, and connectivity-based placement.
Matching Creator:
Customize transistor symmetry using a high level abstraction matching table. Quickly realize transistor placement according to user-defined matching patterns.

Advanced Device Model
Magic Cell (MCell):
Built-in UDSM DRC-correct device generator. Provides flexible device models thus enabling
extremely efficient creation of the devices physical layout from circuit components of a netlist or schematic. Magic Cell reduces the effort for device preparation and provides higher levels of device manipulation. Most importantly, Magic Cell is the only device model that has the ability to deliver handcrafted quality and guarantee zero DRC violations.

Built-in Shape and Grid Based Router
Net Router:
Automatically route single or multiple nets, DRC and LVS clean.
Point to Point Router:
Click on source and target to automatically create a DRC clean route. Or use it in an interactive mode while routing between source and target. Interactive settings for each layer include (1) availability for routing, (2) horizontal and vertical cost functions, and (3) width and space.
Pathfinder:
Interactive single layer DRC-correct path creator. Router follows the mouse in a point and click mode, recognizing same layers and routing around them. Use bind keys to switch between routing layers.
Route by Label:
Using text, or labels, as a guide, routes are automatically created between multiple points.

Hierarchy Manipulation Capability
Manipulate circuit hierarchy on Design Browser or Layout Window in order to optimize layout.

Pattern Recognition Technology
Copy & Associate:
Automatically comb through design database to find matches for selected items. Then automatically copy physical layouts and assign correct connectivity. Drastically reduce time spent on building repeat circuitry.
Pattern Reuse:
Automatically comb through design database to find matches for cells where the hierarchy of the physical layout does not match that of the original schematic. Copy patterns and create new layouts with correct connectivity. Drastically reduce time spent on building repeat circuitry.

Correct-by-Construction
Rule-Driven Editing:
While editing polygons, automatically check, display, and snap to width, space, notch, overlap, and enclosure rules. Increases productivity by reducing need to use
rulers and look up design rules.
Flight Lines & Real-Time Short Detector:
Flight Lines guide user on where to wire. Real-Time short detector displays short errors as
they are created. Both are used to ensure LVS-correct layout results.
Push Wire:
Create a path where you want, push-wire will move same layer routes out of the way.

ECO Capability
Laker compares an ECO netlist with the existing layout and then displays physical and/or logical discrepancies in the Design Browser window. Use automated functions to fix the discrepancies and match the layout back to the schematic.

Layout Debugging and Correction
Auto DRC Correction:
Fix DRC violations automatically, based on user selected area or Laker DRC error viewer. All fixed layout results will keep original connections, so as not to introduce additional LVS violations. Supports Laker-iDRC, Calibre, and Hercules DRC verification tool error reports.
Hierarchical Net Tracer:
Provides a unique feature to trace physical net connectivity through any/all levels of hierarchy.
Verification Explorer:
Seamless integration with third-party industry standard layout verification tools allows the user to browse and debug DRC errors

Magma.blast.v5.0

Magma provides leading software for designing highly complex integrated circuits while maximizing Quality of Results with respect to area, timing and power, and at the same time reducing overall design cycles and costs. Magma provides a complete RTL-to-GDSII design flow that includes prototyping, synthesis, place & route, and signal and power integrity chip design capabilities in a single executable, offering "The Fastest Path from RTL to Silicon"? Magma's software also includes products for advanced physical synthesis and architecture development tools for programmable logic devices (PLDs); capacitance extraction; and characterization and modeling. The company's stock trades on Nasdaq under the ticker symbol LAVA.
The Magma hierarchical design flow includes Blast Fusion for block and top-level physical implementation and Blast Plan Pro for design planning and prototyping. Blast Plan Pro includes three key capabilities in the flow, comprehensive floorplanning, an automated early design planning and prototyping methodology and gate-level partitioning.

Blast Plan Pro抯 comprehensive floorplanning includes IO pad placement, interactive partitioning, soft-block placement and shaping, global-router-driven pin placement and optimization, industry-leading hard macro placement, time budgeting, hand routing for analog or power nets, and automatic power routing with a pushdown capability.

Blast Plan Pro provides a black box methodology for automated early design planning and prototyping.With this methodology, design teams can employ a top-down design approach where the design is floorplanned, partitioned, time budgeted, prototyped and fully implemented at the chip level with Blast Fusion well before block-level RTL is finalized. This methodology can ensure the shortest possible time to market by allowing the designer to start planning and implementing very early in the design cycle and by eliminating the top-level surprises, such as not meeting timing or not being able to successfully route the design, that can often arise late in the design cycle.

Blast Plan Pro抯 fast, high-capacity, gate-level partitioning and prototyping uses a virtually flat, timing-driven placement and partitioning technique that allows designers to perform extensive what-if analysis and quickly and accurately assess the feasibility of their design with respect to timing, physical implementation and electrical effects. Input netlist quality, timing constraints and floorplan alternatives can be quickly analyzed and validated resulting in design problems being found and fixed earlier in the design flow, preventing costly back-end iterations, providing higher confidence that design closure can be achieved, and potentially reducing manufacturing costs by allowing the designer to quickly evaluate floorplans with different aspect ratios and sizes. At any stage in the Magma hierarchical design flow, a design may consist of some mix of gates, RTL, hard macros, black box models, implemented blocks in the form of GlassBox models and implemented blocks in full detail. Blast Plan Pro seamlessly handles this mix of model types and model detail and provides for continuous updating and rebudgeting of top-level timing as blocks in the design progress through the design process until completed.

Key Capabilities in Blast Plan Pro
A successful hierarchical design flow requires a number key technologies and capabilities. Blast Plan Pro fullfills this requirement with its easy to-use GUI, accurate and memory-efficient modeling for hierarchical blocks, high-quality macro placement, partitioning, pin optimization and time budgeting, and support for feed-throughs and top-level routing tunnels.

ZUKEN-CadStar- v10.0

Zuken announces the latest version of the desktop PCB design solution, CADSTAR 10.0, which includes the addition of a large number of intelligent functionalities for schematic, library and PCB design, tighter integration with FPGA design tools, and the introduction of an alternative schematic front-end solution E³.logic.

Design Control
There has been an increased focus on supporting both the engineer and designer to create “right-first-time” designs in shorter time frames. CADSTAR offers users the ability to perform version control at the parts and component level, store parts information in the PCB design, set-up detailed layer stacks for buried and blind via technologies and carry-out impedance controlled routing. CADSTAR 10.0 also includes extended ODB++ output for manufacturing, the ability to highlight nets using multiple colors, plus FPGA design integration and a fully integrated parts library manager in ‘Design Editor’.

Ease-of-use
Ease-of-use with the well-known intuitive workflow has been further improved, to include integration of additional features for assigning any combination of function keys, enhanced layers settings GUI, support of custom colors using the standard Microsoft color dialog, smart update of new software releases and automatic parts index creation. All interactive operations are available while working in a mirrored view in the intelligent place & routing tool, P.R.Editor, for intelligent interactive lengthening or re-lengthening.

E³.logic for CADSTAR
Zuken’s E³.series module, E³.logic, can now be offered as an add-on solution for CADSTAR to further boost users’ productivity. Used as a front-end solution for CADSTAR PCB design it will allow support of multilingual diagrams, multilingual text and Unicode. The use of the E³.Logic database as a back-end solution for CADSTAR PCB design reduces the time spent searching for existing parts, integrates easily with specific MRP, ERP or PDM systems and works with databases that comply with Microsoft's ODBC standard. The CADSTAR E³.logic integration also provides opportunities to directly integrate with other E³.series modules such as E³.cable for complete system level integrated electronics and electrical design.

FPGA Integration
The recently introduced add-on module, CADSTAR FPGA, supports one universal project manager that controls all the design files for simulation, synthesis, place and route and pin assignment to the PCB board, as well as the I/O synchronization between the FPGA device and the PCB board.
This will allow the FPGA designer to forward and backward annotate pin swaps with the PCB layout.

LightTools-v6.0 With SR2

LightTools 6.0 Delivers Expanded Modeling and Optimization Capabilities

LightTools® 6.0, a major new release of the leading illumination design and analysis software from Optical Research Associates (ORA®), delivers an even broader set of system modeling tools and further improves its unique and powerful optimization capabilities. For example, LightTools now includes a user-defined optical properties feature that provides tremendous flexibility in creating specialty optical components. This allows modeling of application-specific, proprietary elements such as specialty polarization components, grating components (with efficiency calculations), scattering surfaces (including anamorphic scatterers) and coating definitions. In addition, LightTools 6.0 allows modeled elements to be immersed in one another in multiple levels – a capability needed for modeling the embedded phosphor and epoxy covering in an encapsulated LED, for example.

The LightTools optimization module, available in beta form in previous LightTools releases, has already proven to be a widely applicable feature that can automatically find optimal illumination design solutions, saving the designer days or even weeks of effort that might be needed to manually explore the design space. LightTools 6.0 brings the first formal release of the optimizer and expands it in several important ways. In particular, it now permits optimization of a given illumination distribution (e.g., uniform or Gaussian) while simultaneously maximizing optical power. LightTools also adds functionality for evaluating how sensitive a system is to variations in specific parameters. This can be useful for selecting variables before beginning optimization, and even enables some basic tolerance analysis computations.

Cadence-MMSIM-V6.2 For LinUx86 &Win

Cadence Design Systems, Inc. (NASDAQ: CDNS), the leader in global electronic-design innovation, unveiled Cadence(R) Virtuoso(R) Multi-Mode Simulation (release MMSIM 6.2), the electronic design industry's first end-to-end simulation and verification solution for custom IC that uses a common, fully integrated database of netlists and models to simulate analog, RF, memory, and mixed-signal designs and design blocks. This breakthrough allows designers to switch from one simulation engine to another without compatibility issues or interpretation impacts, so consistency, accuracy, and design coverage are improved, while cycle time and risk are reduced. The overall result is lower cost of adoption, support, and ownership, and faster time to market.

Virtuoso Multi-Mode Simulation is tightly integrated with the new Virtuoso custom design environment, enabling a complete design-to-verification methodology. In addition, Virtuoso Multi-Mode Simulation provides an innovative and cost-efficient token-based licensing model that allows designers to optimize their usage of different simulation technologies. This model significantly reduces the adoption and support costs typically associated with using multiple simulation technologies from different vendors.

"IBM Global Engineering Solutions deals with a broad range of designs every day, from high-end foundry devices to memories, SERDES, standard cells, I/Os, cores and microprocessors. We regularly use Virtuoso Spectre Circuit Simulator, Virtuoso Spectre XL for RF design, Virtuoso UltraSim and Virtuoso AMS Designer simulators for circuit simulation, RF analysis, and full chip mixed signal verification," said Mark Merrill, Director of IBM Silicon Solutions Engineering and IP Development. "Cadence Multi-Mode Simulation, based on common technology and infrastructure, has provided our designers with a reliable verification solution improving productivity and reducing support costs."

"National Semiconductor uses the complete Cadence Virtuoso Multi-Mode Simulation components, so we see immediate benefits to having an integrated, easy-to-choose simulation model," said Bill Meier, Senior CAD Manager of National Semiconductor. "This solution has enabled thorough verification throughout the design cycle of our leading edge analog products like power management, data converters, and communications interfaces."

"The ground-breaking Cadence Virtuoso Multi-Mode Simulation enables verification throughout the design cycle, across design teams, and even across device types," said Charlie Giorgetti, corporate vice president of marketing for Virtuoso and Allegro Platforms at Cadence. "Customers demand front-to-back design solutions for advanced design. Virtuoso Multi-Mode Simulation addresses design verification challenges for the entire spectrum of custom IC designs at various design domains while being tightly integrated with the new Virtuoso custom design environment, enabling a complete design-to-verification methodology."

Virtuoso Multi-Mode Simulation Supports Kits
The new Virtuoso Multi-Mode Simulation supports the recently released Cadence AMS Methodology Kit, RF Design Methodology Kit, and Low Power Methodology Kit. All three kits offer advanced methodologies and best practices using, among other things, Cadence Virtuoso Multi-Mode Simulation for verification.

What's New in Virtuoso MMSIM 6.2—Tiered Enhancements
Virtuoso MMSIM 6.2 provides a holistic, integrated simulation solution and shared licensing model that better meet diverse customer needs. This solution includes Virtuoso Spectre Circuit Simulator, Virtuoso UltraSim Full Chip Simulator, and Virtuoso AMS Designer. Each of these simulators includes tiered configurations with enhancements tailored to specific levels of design complexity. All are tightly integrated into the Virtuoso Platform Analog Design Environment.

Cadence Virtuoso Spectre Circuit Simulator L

Fast, accurate SPICE-level simulation; optimized engine provides up to 3x performance improvement over traditional SPICE tools
Enhanced Monte Carlo analysis reduces simulations by a factor of up to 10x
Virtuoso Spectre Circuit Simulator XL

Integrated analog, RF and high-speed IC simulation capabilities
Enhanced frequency-domain mutli-rate harmonic balance engine for fast, accurate simulation of high dynamic range, weakly non-linear RF circuits
Patented time-domain shooting algorithm optimized for highly non-linear circuits
New flow for analysis of analog noise and jitter analysis in phase-locked loops, the root cause of silicon re-spins in many mixed-signal SoC designs
Virtuoso UltraSim Full-Chip Simulator L

Fast, high-capacity, SPICE-accurate transistor-level simulation for pre- and post-layout verification at block- and full-chip level for analog, mixed-signal, RF, memory and SoC designs
Virtuoso UltraSim Full-Chip Simulator XL

High-performance digital solver for fast verification of multi-million-transistor custom digital designs with up to 10X better performance
Easy-to-use flow for electromigration and IR drop analysis supports electrical verification of memories and large analog/mixed signal designs
Virtuoso AMS Designer

Mixed-signal simulation with easy access to Virtuoso Spectre L, Virtuoso Spectre XL, Virtuoso UltraSim L and Virtuoso UltraSim XL when needed
Enhanced mixed-signal RF with integration to Virtuoso Spectre XL
Significant performance improvements when used with Virtuoso UltraSim XL for SoC verification

Cadence-ASSURA- V3.17 for Linux

Assura™ Design Rule Checker (DRC) is part of the design verification suite of tools within the Virtuoso® custom design platform. Assura DRC is a full-featured tool that supports both interactive and batch operation modes and utilizes hierarchical processing for fast, efficient identification and correction of design rule errors in even the most advanced designs.

Key benefits

Simplifies design process with a common database for data transfer within the Virtuoso custom design platform
Accelerates design-to-volume with production-proven interactive design rule checking
Reduces re-spins by eliminating design rule errors before tapeout
Ensures fast, silicon-accurate custom design with an integrated silicon verification and analysis flow within the Virtuoso custom design platform


Assura™ Layout vs. Schematic (LVS) Verifier is part of the design verification suite of tools within the Virtuoso® custom design platform. Assura LVS ensures that the layout connectivity of the physical design matches the logical design represented by the schematic or netlist before tapeout by automatically extracting devices and nets formed across layout hierarchy and comparing them to the schematic netlist. Assura LVS provides fast, efficient verification in both interactive and batch mode.

Key benefits

Simplifies design process with a common database for data transfer within the Virtuoso custom design platform
Accelerates design-to-volume with production-proven interactive LVS debugger
Reduces re-spins by eliminating connectivity and mismatch errors before tapeout
Ensures success in analog mixed-signal design with support of mixed netlist and special devices

SoC ENCOUNTER RTL-to-GDSII SYSTEM v7.1 (c) Cadence

Designers of today's SoCs must manage shrinking geometries, increasing design sizes, and growing complexity. As a result, the technical challenge has become how to account for the effects of interconnect across the entire chip—from the outset of the implementation cycle. Additonally, electronics makers need a design system that can deliver the highest quality of silicon (defined as timing, area, and power with wires) along with accurate verification, signal-integrity aware routing and the latest low-power design and yield capabilities, which are critical for advanced 65nm and 45 nm designs.

Cadence SoC Encounter system addresses these requirements within a system that combines RTL synthesis, silicon virtual prototyping, and automated floorplan synthesis, clock network synthesis, design for manufacturability and yield, mixed-signal support, and nanometer routing. Optimized to support 130nm to 45nm designs, it enables full-chip implementation in a single system. SoC Encounter allows engineers to synthesize to a flat virtual prototype implementation—including full-chip, routed wires—at the beginning of the design cycle. Engineers have an early, accurate view of whether the design will meet its targets and be physically realizable. They can then choose to either complete the final implementation or to revisit the RTL design phase. The SoC Encounter system also supports advanced timing closure and routing, as well as signoff analysis engines for final implementation.

SoC Encounter boosts the productivity of design teams, helping them to manage design complexity, and get products to market faster. The SoC Encounter system is available in L, XL, GXL offerings.

Key Benefits:
Combines RTL synthesis, silicon virtual prototype and full-chip implementation in a single, silicon-proven system to achieve timing closure on complex designs
Provides fast, accurate and flexible feasibility analysis—which combines an automated floorplan synthesis and ranking system that enables rapid exploration of the design space with handoff to the physical implementation flow—for a predictable path to design closure
Delivers huge productivity gains through a high-capacity, high-throughput and highly integrated solution that can handle 50M+ gate designs in 130nm process technologies or below
Supports multiple implementation styles with built-in fast power planning, relative floorplaning, and signal integrity analysis
Supports multiple methodologies for flip-chip implementation with automatic RDL routing and 45 degree support, thereby promoting the concurrent design of chip and package
Proivdes highly integrated and consistent process variation fixing with the SSTA solution (includes In-the-Die, Die-to-Die, and Random variation support, block-based and path-based modes, standardized statistical ECSM library models, and characterization support
Incorporates the latest yield and low-power design capabilities for advanced 65nm and 45nm designs

AUTOFORM-MASTER-V4.1.1

the new features and enhancements provide the following main benefits:

The release of version 4.1.1 supplements the June release of version 4.1 with important enhancements offering increased accuracy and efficiency. This new release significantly enhances the performance of the core solver and improves the accuracy of the results.

The newly introduced adaptive mesh de-refinement for higher accuracy has a substantial effect on the simulation results. The accurate simulation results, in particular the precise stress distribution, are important for accurate springback calculation. As a result, the users can rely on an accurate final validation of tool and process layout, including springback simulation and springback compensation – the challenging topics in the sheet metal forming industry.

Accurate Springback Calculation and Springback Compensation: AutoForm's new springback feature automatically modifies tooling surfaces based on a precise springback calculation. Die-face engineers can directly take into account springback results and compensate the appropriate tool geometry. The compensated tool geometry is automatically used as new input for rapid and accurate tooling validation. As a result, more reliable process layouts are realized during early planning phases -- as AutoForm springback compensation minimizes the risk of later, costly changes of tooling or processes due to springback effects.

Precise Geometry Modelling: Significant improvements in geometry modelling are achieved by introducing morphing technology. By modifying wall angles, unfolding part areas and performing in-plane modification of details, keeping the regions outside of the morphing untouched, the user can easily evaluate the best geometry model and optimize the process.

More Efficient Die Development Process: The die development process can be shortened considerably using the new substitution and offset skins provided by AutoForm 4.1.1 Even the original, imperfect surfaces can be substituted by a watertight skin early in the development process. Watertight skins are required for CAD solid design. As a result, solid die design can be started at an earlier stage. Moreover, an additional skin, offset by a large value, can be generated fully automatically. Such offset skins are required for the casting model's solid design. Consequently, the die castings can be launched earlier, reducing the lead time by several weeks.


Accurate Forming Forces: AutoForm 4.1.1 is able to calculate accurate forming forces. Knowing the exact forming force, the user can define the adequate press equipment required for reliable production, at an early stage of the development process.

Ptc-Cadds5i-r14.4

Powerful Design Graphics Capability
CADDS 5 Release 14 now offers the ability to design in a full 3D explicit shaded environment. This powerful tool enables new levels of productivity in design and visualization. It provides a better understanding of complex design scenarios that help to eliminate misunderstandings and interferences by visualizing a true representation.
Robust and Proven
CADDS 5 has a robust and proven software modeling capability across a wide range of industries and projects. This is complemented by integration with the Optegra Workgroup data management solution for control and security of data.
3D View Clipping and Zoning
The new shaded environment is complimented by the capability to clip 3D views to visualize only those items within, or crossing, the defined clip box. This greatly reduces the dataset the user has to manipulate when working with complex designs. Working in both part and assembly mode, clipping can be invoked on individual or multiple views with different clip extents in each view.
Hidden Line Removal (HLR)
When selecting the HLR dataset, marked entities may now be included or excluded from the process. Clipping now respects all three view planes and offers a ‘Within’ and ‘Crossing’ clip boundary selection to provide greater flexibility. Depending on the view, you can choose to include or exclude a particular entity for each view when multiple views have been selected. The ability to save and restore View States in the assembly environment helps ensure the correct view status is taken when updating an HLR view. The user is now informed if attempting to update the HLR with an incorrect View State.

PTC-Optegra-V8.0

Optegra the workgroup data management solution for CADDS
5i provides an open, distributed information environment that
helps manufacturers flexibly and transparently manage,
control, and distribute all types of CADDS 5i and other
non-CAD related product development information.

The unique Optegra architecture allows information consumers
- from engineering to IT to sales and marketing - to browse,
locate, and access any information from desktop PCs and
workstations.


No matter where the data or users reside, up-to-date information is
available - from initial concept to product retirement.

Engineers describe and understand designs in terms of assemblies,
bills-of-material and 3D product multi-user CADDS 5i Concurrent
Assembly environment. It allows designers to dynamically create, view
, and manipulate a single master product model, assess assembly
structures and 3D product views.

ICEM-Surf-V4.7 (C) PTC

ICEM Surf provides breakthrough technology enabling users to produce world-class aesthetic products in today's competitive, global markets. Acknowledged as the premier system for the creation and development of Class A surfaces, ICEM Surf bridges the demands of aesthetic designers and production engineers from visualisation right up to tool and die designers.

The flexibility of ICEM Surf results in high-quality surfaces required in today's design environment, while substantially reducing overall design time. Product development teams using ICEM Surf leave the traditional process behind. ICEM Surf's integrated solutions enable users to implement a new, more efficient method of product development called Virtual Modelling. Stylists and engineers work out design treatments dynamically on screen and immediately see the aesthetic, as well as the engineering, implications of their ideas.

ICEM Surf also has special functionality to painlessly handle the input of digitised physical models. Surface models can be reverse engineered from ordered or unordered (point clouds) digitised data in a fraction of the time compared to other systems. Special diagnostic tools guide the user to form the correct balance between surface smoothness and adherence to the digitised data.

ICEM Surf supports the direct modelling techniques that optimise the update cycles in design and engineering. After creating an initial shape, the user can concentrate on developing the shape through Direct Modelling, operating on surfaces or even directly on scans (point clouds). As the scans or surfaces are directly manipulated, all diagnostics like cross sections or split lines are dynamically updated. With ICEM Surf you always see what you get.

By using ICEM Surf's Global Modelling function, whole detailed models can be modified in total – interactively and dynamically – giving the aesthetic designers an interactive tool to work out a design solution. With the new Unified Modelling approach, you can model all different kinds of entities with the same functionality, without even thinking about their geometric nature. Engineering can adapt structural surfaces to the modified aesthetic surface effortlessly through ICEM Surf’s Feature Modelling function.

And with simultaneous real-time analysis, you can monitor reflection lines, curvature, or deviation from reference data dynamically as you manipulate surfaces. This approach results in unparalleled surface quality and enables designers to converge on production quality surfaces in a fraction of the time that other systems would require for the same task.

Last but not least, ICEM Surf also takes you into Virtual Reality. The rendering module provides advanced rendering functions and photo-realistic images that give the designer a realistic view of the model for presentations and design reviews. You may use stereo mode for 3D visualisation of your CAD model, and real-time renderer for continuous assessment of your modifications in a realistic environment, while continuing to model the geometry.

Based on these techniques, ICEM Surf is the tool of choice in the automotive, tool and die, and product design industries where aesthetic design concepts must be implemented in harmony with product functionality. ICEM Surf allows the designer to create and visualise ideas freely. But most importantly, it allows an interactive environment for the collaboration of the designer and the product engineer. Through a comprehensive set of direct and standard CAD interfaces, ICEM Surf fits easily into any CAD environment.

With ICEM Surf, your product development teams can combine artistic style and engineering performance while developing fully feasible, aesthetic designs faster and with higher quality than with any other CAD system on the market today!

So ICEM Surf will lead to more efficiency if it is used as the platform system for freeform surfacing in any existing CAD/CAM environment.

With ICEM Surf, product styling is no longer held hostage by its engineering!

CST-Studio-Suite-V2008

The electromagnetic simulation software CST STUDIO SUITE™ is the culmination of many years of research and development into the most efficient and accurate computational solutions to electromagnetic design. It comprises the following modules:

CST DESIGN ENVIRONMENT™
CST DESIGN ENVIRONMENT™ (CST DE) is the access point to the CST STUDIO SUITE™

CST MICROWAVE STUDIO®
CST MICROWAVE STUDIO® (CST MWS) is a specialist tool for the fast and accurate 3D EM simulation of high frequency problems. Along with a broad application range, CST MICROWAVE STUDIO® offers considerable product to market advantages: Shorter development cycles - Virtual prototyping before physical trials - Optimisation instead of experimentation.

CST DESIGN STUDIO™
CST DESIGN STUDIO™ (CST DS) provides a powerful design environment in which the results from diverse simulators can be combined and analysed.

CST EM STUDIO™
CST EM STUDIO™ (CST EMS) is an easy-to-use tool for the analysis and design of static and low frequency structures.

CST PARTICLE STUDIO™
CST PARTICLE STUDIO™ (CST PS) is a highly specialised tool for the fully consistent simulation of free moving charged particles as in electron guns, cathode ray tubes, ... .

Solvaco-TCAD-SCAD-SmartSpice-AMS-V 2007

Silvaco International, a leading vendor of commercial TCAD software, today announced that Lite-On Semiconductor Corporation (LSC), a leading manufacturer of image sensors and discrete power devices, has standardized on the Silvaco TCAD process and device simulation flow to develop its next generation power devices.

“We chose the Silvaco TCAD solution for its broad functionality, reliable performance, experienced , straightforward business model and the clear Stanford-based roadmap for the future”, said C.C. Chen, executive VP, Discrete and Analog Division, for LSC. “We were able to simulate our existing processes and devices using Silvaco TCAD software without re-calibrating our existing Stanford-based model coefficients.”

Silvaco provides advanced TCAD technologies based on the latest physical models for process and device simulation. Customers of Silvaco TCAD software create leading-edge MOS processes and devices, SOI, power devices, and optical semiconductors for sensors, display panels, LEDs and lasers. Customers are switching to Silvaco TCAD from other TCAD because they do not have to recalibrate their model coefficients, re-establish their process and device simulation flows developed over many years, or learn new software.

About Silvaco TCAD Tools

ATHENA Process Simulation Framework enables process and integration engineers to develop and optimize semiconductor manufacturing processes. ATHENA provides an easy to use, modular, and extensible platform for simulating ion implantation, diffusion, etching, deposition, lithography, oxidation, and silicidation of semiconductor materials. It replaces costly wafer experiments with simulations to deliver shorter development cycles and higher yields.

ATLAS Device Simulation Framework enables device technology engineers to simulate the electrical, optical, and thermal behavior of semiconductor devices. ATLAS provides a physics-based, easy to use, modular, and extensible platform to analyze DC, AC, and time domain responses for all semiconductor based technologies in 2 and 3 dimensions.

Virtual Wafer Fab is an integrated environment of TCAD software to automate and emulate physical wafer manufacturing. These integrated tools facilitate the input, execution, run-time optimization, and results processing of TCAD simulations into one flow managed through a common database.

November 0day softwares

2007-11-30 ALGOR.Designcheck.v21.0
2007-11-27 CNCKAD V8.5 (C)Metalix
2007-11-26 SmartDraw.2008.ISO
2007-11-25 Graphisoft.ArchiCAD.v11.Hotfix.1114.Upgrade.Only
2007-11-24 Adina V8.4.2
2007-11-23 Dynaform.5.6 (C)ETA
2007-11-22 GibbsCAM.2007.v8.7.6
2007-11-21 ESI.Procast.v2007
2007-11-20 SolidWorks 2008 Office Premium for 64 BIT
2007-11-19 Intel.Cluster.Toolkit.Compiler.Edition.v3.1.ISO
2007-11-18 Dassault.Systemes.Catia V5R18 Sp2 for win32&win64
2007-11-17 MSC.SimDesigner.for.Catia.v5R17.R2.WiNNT2K
2007-11-15 MSC.Patran.v2007.R1B.WiNNT2K
2007-11-12 RiB_Stratis_v11.3_GERMAN
2007-11-12 MSC.SIMOFFICE.R2.1
2007-11-11 CSI_ETABS_9.16_UPDATE
2007-11-11 CSI_SAP_2000_V11.07_UPDATE
2007-11-11 Pointwise.Gridgen.v16.0.R2.LINUX&MACOSX&win
2007-11-10 GibbsCAM.2007.v8.7
2007-11-09 CADVANCE.V12.32
2007-11-07 Imold 2007 v8 forSolidworks2008
2007-11-06 EMS-I_GMS_V6.0_DC20070807
2007-11-05 Macrovision_AdminStudio_v8.6_Enterprise_Edition
2007-11-05 Combit_Relationship_Manager_v2007_BiLiNGUAL
2007-11-04 CGTECH_VERICUT_V6.1.2
2007-11-03 Dassault .Systemes.Catia V5R17 Sp7 for win32&win64
2007-11-02 Telelogic.Rhapsody .v7.1 for Win &Linux
2007-11-02 AutoCAD.Civil3D.2008.GERMAN
2007-11-02 DesignCAD.3D.Max.v18
2007-11-01 Dassault.Systemes.Catia.P3.V5R18 with SP1

ESI-Visual-Environment-v3.0.1

Visual Environment is the first brick of the new environment for ESI Group’s leading
crash simulation software. Visual Environment has been built by merging ESI Group’s
former environment solution into EASi’s inherited technology. The embedded data
model offers a very versatile environment where new applications and interfaces can
easily be implemented.

Visual-Mesh is a complete meshing tool which supports CAD Import, 2D and 3D
Meshing and Editing features. Some of the features which work on ‘mesh only’ will be
available in Visual-Crash PAM context.

Visual-Crash PAM (VCP), which is one of the contexts in Visual-Environment,
provides PAM-CRASH users with fast iteration and rapid model revision process, from
data input to visualization for crashworthiness simulation and design. This environment
provides quick model browsing, advanced mesh editing capabilities and rapid graphical
assembly of system models. VCP allows graphical creation, modification and deletion
of contacts, materials, constraints, control cards and all crash entities. In VCP, you are
provided with tools for checking model quality and simulation parameters prior to
launching calculations with the Solver. Using these tools helps in correcting errors and
fine-tuning the model and simulation before submitting it to a solver, thus saving time
and resources.

Visual-Safe is a context in Visual-Environment, dedicated to Safety utilities. High
productivity tools such as advanced dummy positioning, seat morphing, belt fitting and
airbag folding are provided in this context.

Visual-Safe MAD (VSM) is a complete, efficient and productive CAE environment for
multi-body and finite element occupant safety simulations using Madymo. It utilizes the
multi-window/multi-model/multi-application environment of Visual-Environment
very efficiently. It provides complete flexibility of working for both the experienced
and the novice Madymo users alike. It incorporates a vast database of customer
requirements and feedback gathered over a decade.

Visual-Medysa guides PAM-MEDYSA 2G users in building system models for design
optimization and performance validation of complex mechanical systems. Mechanical
systems such as engine, tires, chassis, suspensions, and machinery transmissions, can be
modeled with ease in this environment.

High Velocity Impact (HVI) simulation is used to analyze the dynamic behavior of
materials under very high speed impacts. Visual-HVI supports PAM -SHOCK HVI
user in modeling such material data easily. This typically finds applications in
aerospace where we need to understand the damage suffered by a spacecraft when it
encounters space debris, such as micro-meteoroids.

Visual-Viewer is the new generation Post Processing tool with state-of-art Plotting
utility. This caters to the requirements of the CAE community. Visual-Viewer is built
on the multi page/multiplot environment, which enables the user to group his data into
pages and plots. Visual-Viewer is designed with intuitive and sleek user interface with
Windows look and feel. Complete session can be re-run without loss of any data.

Visual-Viewer is completely command driven which enables the user to execute
commands at ease. Visual-Viewer is completely built on multi-page and multi-plot
environment. The user has the freedom to create any number of pages and to have upto
16 windows in a single page. These windows can be plot, animation, video, model or
drawing block windows. The entire snapshot of the product can be saved as a template
and restored any time.

Visual-Process Executive’s Process-oriented philosophy brings a compelling
advantage to PAM-CRASH users to build processes quickly by customizing GUIs and
to execute them.

Visual-Crash Dyna (VCD) provides advanced capability and fast-guided model
building of LS-DYNA solver. Using Visual-Environment multi-window/multimodels/
multi-application environment, with visual verification, complete model
building activity can be performed efficiently.

Visual-Seal provides advanced capability and fast-guided model building of Seal
model. Using the Visual-Environment multi-window/multi-model/multi-application
environment, with visual verification, complete model-building activity can be
performed efficiently.

Visual-Life Nastran (VLN) is a comprehensive, integrated environment for Nastran
simulations with powerful enterprise capabilities. VLN is a ‘high-performance’
software to manage and assemble large and complex finite element system models for
Nastran, NVH and durability analysis with its unique multi-window / multi model
environment providing high productivity with powerful visualization and model
browsing.

Visual-Crash Rad (VCR) (Beta) provides advanced capability and fast-guided model
building of RADIOSS solver. Using Visual-Environment multi-window/multimodels/
multi-application environment, with visual verification, complete model
building activity can be performed efficiently.

FEKO-Distrib-V5.3

FEKO Suite 5.3
Major highlights include

* OPTIMISATION: Complete re-design and re-implementation of the optimisation process and workflow.
* NON-RADIATING NETWORK ANALYSIS: A general network implementation for the inclusion of multi-port S- Z- and Y- parameter-based networks.
* Geometrical Optics (GO): A new implementation for the analysis of electrically large dielectric bodies e.g. dielectric lens antenna.

User Interface

* Stand-alone command-line driven tool for CAD model re-evaluation and meshing.
* POSTFEKO GUI available on the 64-bit x86_64 platform.
* Selective importing from existing CADFEKO models.
* GID mesh import.

Kernel

* Geometrical Optics for dielectrics: A new method is available for the analysis of large dielectric structures, particularly for lens antenna applications.
* General non-radiating networks: Multiple cascaded general multiport networks (based on S- , Y- and Z- matrix representations) may be included in the FEKO model. Current interaction is taken into account at the network-geometry connection points.
* Fast near-field calculations for the MLFMM: Dramatic reduction in time required for computation of the near-field at many points for large models.
* Waveguide port excitation available on models that include dielectric parts: Available for MoM/SEP or FEM models or where the CFIE (combined field integral equation) is used on metallic objects.
* UTD extended: Provision for connection of multiple plates at a single edge.
* Support for the indexed point-arrays in EDITFEKO: Expansion to allow for point-array and variable-array based definition of polygon and polygonal plate geometry primitives in scripted geometry definitions with no limitation on the number of points used.

Improved parallel MLFMM efficiency: Run-time improvement due to load balancing and improved parallel communication schemes.
* Improved memory allocation on 32-bit Windows operating systems: The maximum memory allocation has been expanded by modification of the Windows DLL handling code.


Licencing

* Extension of the concept of a ”preferred” licence to node-locked licences.
*
Provision for the usage of a node-locked licence on a computer when network / nameserver access is not available: When a licence file containing mixed floating/node locked licences is used, network access is no longer required.