IPM.Petroleum.Expert.v7.10.Build143 license

IPM Products

Petroleum Experts develop the Integrated Production Modelling software (IPM). IPM models the complete oil or gas production system including reservoir, wells and the surface network.

The IPM suite of tools: GAP, PROSPER, MBAL, PVTP, REVEAL and RESOLVE can be run together seamlessly, allowing the engineer to design complete field models. The models can include the reservoir tanks, all the wells and the surface gathering system. IPM can model and optimise the production and the water or gas injection system simultaneously.

With the Reservoir, Wells and Complete Surface Systems model completed and the production history matched, the production system can be optimised and production forecasts run.

The unique global optimisation approach permits the engineer to determine the optimum setting to maximum production or revenue, taking account of all constraints that are set in the system. These results can then be used to implement adjustments at the field level to achieve the optimisation goals.

There are literally several thousand fields worldwide having their production managed and optimised using IPM. Here is a recent article published in the E&P magizine using the IPM technology on the Draugen field in Norway. E&P Article

All common naturally flowing well configurations, including multi-lateral, whether naturally flowing or with artificial lift can be modelled and optimised together.

With the use of RESOLVE and OpenServer the IPM approach has been extended to connecting the PETEX software to third party software such as Reservoir Simulators and Process Simulators.

These products form a suite of complementary tools assisting engineers to improve their reservoir simulations by describing and modelling a production system more accurately.

Paradigm.Sysdrill.v2009 license

Paradigm Sysdrill is designed to reduce drilling risk and cost by enabling the drilling engineer to model every phase of well bore construction within a single application. The high level of engineering analysis available in Sysdrill enables users to identify and eliminate potential design problems with flexibility and accuracy.

The Sysdrill application suite includes well planning, survey management, anti-collision, torque and drag, hydraulics, casing design, cementing, and well control in a single integrated package.


Integrated well planning, drilling engineering analysis and visualization allows drilling engineers to perform quick and accurate well design by incorporating the geological model.

Paradigm Sysdrill is designed to reduce drilling risk and cost by enabling the drilling engineer to model every phase of well bore construction within a single application. The high level of engineering analysis available in Sysdrill enables users to identify and eliminate potential design problems with flexibility and accuracy.

The Sysdrill application suite includes well planning, survey management, anti-collision, torque and drag, hydraulics, casing design, cementing, and well control in a single integrated package.
Improve well planning accuracy
Target selection from seismic, reservoir, and log data for reduced well planning cycle times, improved wellbore placement, and reduced drilling risk
Geometric and engineering constrained well planning to ensure wellbore drillability
Positional uncertainty modeling to allow target sizing and survey tool program design
Improve drilling safety
Survey management and anti-collision analysis minimize the possibility of collision
Project-ahead-during-drilling and sidetracking help to determine how best to drill ahead and optimize wellbore positioning within the reservoir
Casing and mud design to ensure wellbore hydraulic integrity
Reduce drilling risk
BHA (bottom hole assembly) design to allow wellbore drillability
Fatigue analysis enables prediction and avoidance of mechanical failure of the drill string
Pressure data extractions along the wellbore to allow for avoidance of pressure hazards, improved casing seat placement, and optimized hydraulic design

Components of Sysdrill 2009:
Sysdrill Casing Design
Sysdrill Cementing
Sysdrill Designer
Sysdrill Director®
Sysdrill DirectorGeo™
Sysdrill Hydraulics
Sysdrill Torque and Drag
Sysdrill Well Control

Note: The following Paradigm applications can be used with Sysdrill to achieve extended workflows:
Geolog® Geosteer™
OpsLink®
VoxelGeo™

IAR Embedded Workbench for ARM 5.4

IAR Systems introduced Version 5.40 of IAR Embedded Workbench for ARM. Version 5.40 featurees new debug capabilities for ARM Cortex-M3 processors that were previously only available in dedicated devices and costly debug probes. In addition, Version 5.40 supports source code compliance checking to the MISRA-C:2004 standard, for high integrity applications such as automotive as well as support for the ARM Cortex Microcontroller Software Interface Standard (CMSIS).
News in the current product version Version 5.40 of IAR Embedded Workbench for ARM includes the following new and enhanced functionality:
Information Center A new, web based navigation system that gives easy access to tutorials, product documentation, and example projects. Select Help>Information Center to display the Information Center.
Cortex-R4
Support for code generation and debugging of ARM Cortex-R4 cores.
Cortex-M0

Support for code generation and debugging of ARM Cortex-M0 cores. Debugging on Cortex-M0 hardware is supported using the J-Link probe.
J-Trace for Cortex-M3 Using the J-Trace for Cortex-M3 debug, the debugger can now take advantage of the ETM trace port available on some Cortex-M3 devices. Instruction trace can be started and stopped based on conditions like code locations and data accesses. This feature requires the J-Trace for Cortex-M3 trace probe.
Direct flash erase and download

Flash erase and download can be performed without starting the debugger.
Debugging multiple images C-SPY is now capable of debugging several independently built images during one debug session. Under Project options>Debugger>Images you specify the location of the images to be downloaded in addition to the current application. There is also a new debugger window called Images where you select for which application debug information will be displayed.
Cortex-M3 data breakpoint enhancements
A data breakpoint in Cortex-M3 is now able to break on a specific value in addition to the address of the accessed variable.
Auto refresh in the debugger memory window
The debugger memory window can be refreshed during program execution, both manually and periodically.
Example projects
Over 1400 example projects for various evaluation boards, including evaluation boards from IAR Systems, Actel, Analog Devices, Aiji Systems, ARM, Atmel, Cirrus Logic, Freescale, Keil, LogicPD, Luminary, Micronas, Nohau, OKI, Olimex, Pasat, NXP, Phytec, ST, Texas Instruments and Toshiba are included in the product installation, see the Information Center, or arm\examples directory.
New device support Support for many new devices are added in this release. Please see update-to-date device list for more details.

The compiler optimizer has been tuned to generate industry-leading code size for Cortex-M3 code. The linker can also now compress initialized data to minimize demands on Flash memory: the compressed data will be automatically uncompressed when moved from Flash to RAM by the startup code.

VECTOR FIELDS OPERA V12

FEA modelling of static and time-varying electromagnetic fields

Opera provides the complete toolchain for electromagnetic design, simulation and analysis of results, for use on 32- or 64-bit Windows and Linux platforms. It consists of a powerful pre-processing environment for creating design models (or importing them from CAD programs), plus a powerful finite element analysis (FEA) solver from our range. Three generic solvers are optionally available:

* static electromagnetic fields (the widely used 'Tosca' tool) - More
* low-frequency time-varying electromagnetic fields - More
* high frequency time-varying electromagnetic fields* - More

Opera can alternatively be purchased in a number of forms optimised for specific design problems:

* linear and rotating machinery design - More
* superconducting magnet quenching - More
* space charge effects from particle beams - More
* permanent magnet magnetisation/demagnetisation - More
* thermal and stress analysis (standalone or coupled) - More
* electric field analysis in conducting-dielectric media - More

*Vector Fields produces a dedicated package for RF and microwave electromagnetic design, Concerto, with FDTD or MoM solvers. The FEA solver used in Opera is optionally available, for design problems where extreme solution accuracy is needed.

Detailed product information

Click on the two- or three-dimensional (2D/3D) Opera module of interest for more information:

Opera 2D
Static fields
Dynamics (low frequency)
Rotating machines
Linear motion
Space charge
Lossy dielectrics
Demagnetisation
Stress and thermal


Opera 3D
Static fields
Dynamics (low frequency)
Rotating machines
Space charge
Thermal
Quench
High frequency
Lossy dielectrics
Demagnetisation

Click here to download the Opera brochure.

How Opera works

Process-Systems-Enterprise-gPROMS-v3.20-license

gPROMS v3.2: modelling, usability and solution power
Powerful custom modelling in a flowsheeting environment
We are pleased to announce the release of gPROMS version 3.2.

V3.2 builds on the new functionality in the previous v3.0 and v3.1 releases, refining and completing some of the many features introduced with the new gPROMS v3 architecture. This takes PSE's aim of providing the world's most powerful custom modelling within a flowsheeting environment a significant step forward.

Apart from the numerous productivity, speed and robustness enhancements, v3.2 contains significant enhancements to the ability to handle discrete logic within the equation-oriented modelling environment, as requested by a number of customers over the years.

Building on gPROMS' already strong capabilities for modelling and optimising both complex physics and discrete operating procedures, each physical model can now invoke discrete logic that is automatically triggered for every instance of the model included in a flowsheet. This allows, for example, gPROMS library models to include sophisticated supervisory controllers, whose execution is completely transparent to end-users.

There are a number of usability enhancements aimed at simplifying the creation and maintenance of complex flowsheets. These range from minor improvements such as the ability to align flowsheet elements to the ability to use text array indices consistently throughout gPROMS, including dialogue specifications.

v3.2 contains significantly-enhanced diagnostics that make information more easily accessible both for model developers and users. These include facilities for diagnosing over-and under specification and making intelligent suggestions for the choice of specification variables. There is improved analysis and assistance for numerical failures during execution, as well as improved information at the flowsheet level during model construction.

For results presentation, a new data export facility provides semi-automated selective export of variables to postprocessing facilities such as MS Excel for - for example - pivot table analysis. In addition to providing formatted output and addition calculations, this helps reduce model size and execution time.

Emphasizing the fact that PSE's development continues to focus on the underlying solution technology for which gPROMS is renowned, there have been some significant enhancements to solution power and efficiency.

Exact model reduction techniques to eliminate inessential equations and variables during solution mean that many classes of problem now run 20% faster than in previous versions and use less memory. Examples from testing to date are a parameter estimation problem that ran in half the time taken in v3.1.5, a typical 20% reduction in memory footprint and, in one case, a reduction in the number of variables by a factor of 40% and simulation time by a factor of 35%.

These improvements allow increases in the number of discretisation points used, in order to improve accuracy, or increases in complexity of flowsheets, while keeping simulation times and memory requirements within acceptable limits.

On the CFD front, an extended Hybrid Multizonal interface now supports FLUENT® multiphase models with or without energy conservation, FLUENT dynamic simulations in two-way mode, FLUENT 2-D models and FLUENT parallel processing in either one or two-way mode.

Cadence software product list

Front End Design Newest Base Release(s) Other recent Base Releases
Encounter ConFRML Technologies CONFRML 8.1, CCD 8.1 CONFRML 7.1, CCD 6.2, CONFRML 6.1
Encounter Test ET 6.2 ET 3.1
Encounter RTL Complier RC 7.1 RC 6.2

Virtuoso Custom Chip Design Newest Base Release(s) Other recent Base Releases
Cadence Chip Optimizer FINALE 6.2 FINALE 6.11, FINALE 6.1, FINALE 2.0
Cadence Space-Based Router FINALE 6.2 FINALE 6.11, FINALE 6.1, FINALE 2.0
Virtuoso AMS Designer IC 6.1.0, IUS 6.1 IC 5.1.41, IUS 5.8, IUS 5.7
Virtuoso Analog Design Environment IC 6.1.0 IC 5.1.41
Virtuoso Aptivia Specification-driven Environment VSDE 4.1 VSDE 3.3
Virtuoso Chip Assembly Router IC 6.1.0 ICC 11.2.41
Virtuoso Chip Editor IC 6.1.0 IC 5.1.41
Virtuoso Layout Editor IC 6.1.0 IC 5.1.41
Virtuoso Layout Editor-Turbo IC 6.1.0 IC 5.1.41
Virtuoso Layout Migrate IC 6.1.0 IC 5.1.41
Virtuoso Layout Suite IC 6.1.0
Virtuoso MultiMode Simulation MMSIM 8.2 MMSIM 6.1, IC 5.1.41
Virtuoso NeoCell Analog Physical Synthesis NEOCELL 3.4 NEOCELL 3.3
Virtuoso NeoCircuit Sizing and Optimization NEOCKT 3.4 NEOCKT 3.3
Virtuoso QRC Extr*** EXT 6.2 EXT 5.1
Virtuoso RET Suite RET 1.7 RET 1.6, RET 1.5
Virtuoso Schematic Editor IC 6.1.0 IC 5.1.41
Virtuoso Spectre Circuit Simulator MMSIM 8.2 MMSIM 6.1, IC 5.1.41
Virtuoso Spectre RF Simulation Option MMSIM 8.2 MMSIM 6.1, IC 5.1.41
Virtuoso UltraSim Full-chip Simulator MMSIM 8.2 MMSIM 6.1, USIM 4.2, USIM 4.1
Virtuoso XL Layout Editor IC 5.1.41

Encounter Digital Chip Design Newest Base Release(s) Other recent Base Releases
CeltIC NDC TSI 7.1 TSI 6.2
ElectronStorm ANLS 7.0 ANLS 6.1, SEV 3.2
Cadence Chip Optimizer FINALE 2.0
Encounter Con***al Technologies CONFRML 7.1, CCD 7.1 CONFRML 6.2, CCD 6.2, CONFRML 6.1
Encounter QRC Extr*** (Fire & Ice QX) EXT 6.2 EXT 5.1
Encounter RTL Complier RCV 7.1 RCV 6.2
Encounter Test ET 6.2 ET 3.1
Encounter Timing System ETS 7.1 ETS 6.2, ETS 6.1
Encounter X SOC 8.1 XAE 6.1, XAE 5.2
First Encounter SOC81 SOC81,SOC61, SOC52
NanoRoute Ultra SOC81 SOC81,SOC61, SOC52
PacifIC Static Noise Analyzer PACIFIC61
SignalStorm NDC TSI 6.1 TSI 5.2
Silicon Ensemble-PKS Optimization SOC 6.2 SOC 6.1
SoC Encounter SOC 6.2 SOC 6.1
VoltageStorm ANLS 7.1 ANLS 6.2, ANLS 6.1

Incisive Emulation Hardware Newest Base Release(s) Other recent Base Releases
Incisive Palladium IXE 5.1 IXE 5.0, IXE 4.0, IXE 3.1
Incisive Xtreme RCC 7.1 RCC 6.3,RCC 6.2, RCC 5.3, RCC 5.2, RCC 5.1, RCC 4.4

Incisive Design Verification and Acceleration Newest Base Release(s) Other recent Base Releases
Design Team Simulator IUS 8.1 IUS 5.8, IUS 5.7
eAnalyzer SPMN 6.0 EANL 5.1, EANL 1.0
FPGA Compiler RCC 6.3 RCC 6.2, RCC 5.3, RCC 5.2, RCC 5.1, RCC 4.4
HDL Simulator IUS 8.1 IUS 5.8, IUS 5.7
Incisive Design Team Manager VMGR 1.4 EMGR 2.02, EMGR 2.0
Incisive Enterprise Manager VMGR 1.4 EMGR 2.02, EMGR 2.0
Incisive Enterprise Simulator IES 6.1 IES 2.0
Incisive Enterprise Specman Simulator IES 6.1 IES 2.0, SPECSIM 1.3
Incisive Formal IFV 6.1 IFV 5.8
Incisive Scenario Builder SPMN 6.0 SBLD 1.1, SBLD 1.0
Incisive Unified Simulator IUS 8.1 IUS 5.8, IUS 5.7
NC-Sim IUS 8.1 IUS 5.8, IUS 5.7
NC-SystemC IUS 8.1 IUS 5.8, IUS 5.7
NC-Verilog IUS 8.1 IUS 5.8, IUS 5.7
NC-VHDL IUS 8.1 IUS 5.8, IUS 5.7
Plan-to-Closure Methodology IPCM 6.1 IPCM 6.0
Specman Elite SPMN 6.1 SPMN 6.0
Verifault IUS 8.1 IUS 5.8, IUS 5.7

Verification IP Newest Base Release(s) Other recent Base Releases
AMBA EVCAMBA 2.2
eVC-AHB ABVIPAHB 1.0
eVC-AXI EVCAXI 1.2
eVC-Ethernet EVCETH 2.2
eVC-PCI EVCPCI 2.11
eVC-PCI Express EVCPCIE 2.2
eVC-USB EVCUSB 2.3 EVCUSB 2.2

Silicon Signoff and Optimization Newest Base Release(s) Other recent Base Releases
Assura (DRC/LVS) Physical Verification ASSURA 3.1.7
Cadence Physical Verification System PVS 6.1 PVS 5.2
Chameleon KCL 4.3 KCL 4.2
Diva Physical Verification IC 6.1.0 IC 5.1.41, ICOA 5.1.41
Dracula Physical Verification IC 6.1.0 IC 5.1.41, ICOA 5.0.33, ICOA 5.2.51, ICOA 5.1.41
ElectronStorm ANLS 6.2 ANLS 6.1, SEV 3.2
MaskCompose KMC 3.8
PacifIC Static Noise Analyzer PACIFIC 6.1
QuickView KQV 4.3.1 KQV 4.3
VoltageStorm Analog ANLS 7.1 ANLS 6.2,ANLS 6.1, SEV 3.2

Manufacturing Models and Implementation Newest Base Release(s) Other recent Base Releases
Cadence Chip Optimizer FINALE 6.2 FINALE 6.11, FINALE 6.1, FINALE 2.0
Cadence Space-Based Router FINALE 6.2 FINALE 6.11, FINALE 6.1, FINALE 2.0
Encounter QRC Extr*** (***erly Fire & Ice QX) ANLS 7.1 ANLS 7.1,ANLS 6.1, SEV 3.2
Virtuoso QRC Extr*** (***erly Assura RCX) EXT 6.2 EXT 5.1
Vituoso RET Suite RET 1.7 RET 1.6, RET 1.5

Allegro PCB & IC Packaging Newest Base Release(s) Other recent Base Releases
Allegro AMS Simulator SPB 16.2 SPB 15.7, SPB 15.5.1
Allegro Design Entry CIS SPB 16.2 SPB 15.7, SPB 15.5.1
Allegro Design Entry HDL SPB 16.2 SPB 15.7, SPB 15.5.1
Allegro Design Publisher SPB 16.2 SPB 15.7
Allegro IC Package Designer SPB 16.2 SPB 15.7, SPB 15.5.1
Allegro IC Package SI SPB 16.2 SPB 15.7, SPB 15.5.1
Allegro PCB Editor SPB 16.2 SPB 15.7, SPB 15.5.1
Allegro PCB Librarian SPB 16.2 SPB 15.7, SPB 15.5.1
Allegro PCB Router SPB 16.2 SPB 15.7, SPB 15.5.1
Allegro PCB SI SPB 16.2 SPB 15.7, SPB 15.5.1
Allegro System Architect SPB 16.2 SPB 15.7, SPB 15.5.1
Cadence 3D Design Viewer SPB 16.2 SPB 15.7, SPB 15.5.1

OrCAD PCB Newest Base Release(s) Other recent Base Releases
OrCAD Capture/CIS ORCAD 16.0 ORCAD 15.7, ORCAD 15.5
OrCAD Layout ORCAD 16.0 ORCAD 15.7, ORCAD 15.5
OrCAD PCB Editor ORCAD 16.0 ORCAD 15.7, ORCAD 15.5
OrCAD Signal Explorer ORCAD 16.0 ORCAD 15.7, ORCAD 15.5
PSpice ORCAD 16.0 ORCAD 15.7, ORCAD 15.5

Cadence SiP Design (System-in-Package) Newest Base Release(s) Other recent Base Releases
Cadence 3D Design Viewer SPB 16.0 SPB 15.7, SPB 15.5.1
Cadence SiP Digital ORCAD 16.0 ORCAD 15.7, ORCAD 15.5
Cadence SiP RF ORCAD 16.0 ORCAD 15.7, ORCAD 15.5

Allegro Design Workbench Newest Base Release(s) Other recent Base Releases
PCB Collaboration Workbench ADW 16.0 ADW 15.7, ADW 15.5
PCB Design Workbench ADW 16.0 ADW 15.7, ADW 15.5
PCB Library Workbench ADW 16.0 ADW 15.7, ADW 15.5

Cadence Design Kits Newest Base Release(s) Other recent Base Releases
Cadence AMS Methodology Kit AMSKIT 6.1 AMSKIT 5.1
Cadence Functional Verification Kit for ARM VKARM01 6.1
Cadence RF Design Methodology Kit RFKIT 5.2
Cadence RF SiP Methodology Kit RFSIPKT 6.1
Cadence Low Power Methodology Kit LPKIT 0.7

CoWare.Processor.Designer 2009

CoWare Processor Designer
Programmable Accelerators for Platform-Driven ESL Design

* Integrated design environment for unified application specific processor, programmable accelerator design and software development tool generation
* Slashes application specific processor and programmable accelerator hardware design time by months
* Eliminates months of engineer-effort for software tool development
* Ensures compatibility of instruction set simulator (ISS), software development tools and RTL implementation
* Software development environment enables application software development prior to silicon availability

CoWare® Processor Designer is an automated, application-specific embedded processor design and optimization environment that slashes months from processor hardware design time and engineer-month from the creation of application processor-specific software development tools. Processor Designer's high degree of automation enables design teams to focus on architecture exploration and application-specific processor development, rather than on consistency checking and verification of individual tools.

Processor Designer dramatically accelerates the design of both custom processors and programmable accelerators, including the application-specific instruction set processors (ASIPs) that are increasingly essential to convergent system-on-chip (SoC) functionality. Processor Designer is used to develop a wide range of processor architectures, including architectures with DSP-specific and RISC-specific features as well as SIMD and VLIW architectures.

Processor Designer's generated software development environment enables the commencement of application software development prior to silicon availability, thus eradicating a common bottleneck in embedded system development.

The key to Processor Designer's automation is its Language for Instruction Set Architectures, LISA 2.0. In contrast to SystemC, which has been developed for efficient specification of systems, LISA 2.0 is a processor description language that incorporates all necessary processor-specific components such as register files, pipelines, pins, memory and caches, and instructions. It enables the efficient creation of a single "golden" processor specification as the source for the automatic generation of the instruction set simulator (ISS) and the complete suite of software development tools, like Assembler, Linker, Archiver and C-Compiler, and synthesizable RTL code. The development tools, together with the extensive profiling capabilities of the debugger, enable rapid analysis and exploration of the application-specific processor's instruction set architecture to determine the optimal instruction set for the target application domain. Processor Designer enables the designer to optimize instruction set design, processor micro-architecture and memory sub-systems, including caches.

Processor Designer's use of a single high-level processor specification ensures the consistency of the ISS, software development tools and RTL implementation, eliminating the verification and debug effort necessitated by multiple, independently-created models.

Operating at a high level of abstraction, Processor Designer not only eliminates the time and cost inherent in HDL-based processor design and manual tool development, but also enables hardware and software designers to customize the instruction set to their needs.

ALDEC-Alint-2009

Design Rule Checking
ALINT™ is an RTL design analysis tool that identifies design issues early in the development cycle. VHDL, Verilog® or mixed-language designs are checked for coding inconsistencies, design structure issues, synthesis, simulation, and clock and reset issues prior to simulation and synthesis. ALINT significantly reduces verification time for complex FPGA and ASIC designs, results in uniform, reusable and reliable code and reduces the risk of costly ASIC re-spins. Comprehensive rule sets are available for VHDL, Verilog and mixed-language designs. ALINT includes powerful utilities for rule management, violation analysis, and debugging.

Top Features

* Fast design analysis of complex ASIC/FPGA-SOC designs
* Comprehensive set of rules to check most complex design issues
* Integrated results analysis and debugging environment
* Supports IEEE VHDL, Verilog and mixed-language designs
* Supports Custom Design Rules
The increasing adoption of large, high-pin-count and high-speed FPGA devices means that right-first-time printed circuit board (PCB) design practices are more essential than ever for ensuring correct system operation. Typically, the PCB design takes place concurrently with the design and programming of the FPGA. Signal and pin assignments are initially made by the FPGA designer, and the board designer must correctly transfer these assignments to the symbols used in their system circuit schematics and board layout. As the board design progresses, pin reassignments may be needed to optimize the PCB layout. These reassignments must in turn be relayed back to the FPGA designer so that the new assignments can be processed through updated placement and routing of the FPGA design. To overcome these challenges, Zuken and Aldec provide an integrated design environment to support these design flows.

Etap-PowerStation-v7.0(ETАP Pоwer Stаtiоn, ETАP Enterprise Sоlution fоr Electricаl Pоwer Systеms)

Delivering Unmatched
Speed, Precision, & Reliability
Etap.PowerStation.v7.0
Release 7.0 of the ETAP Enterprise Solution brings design and analysis innovation to a new level of advancement and provides the platform upon which future ETAP innovation will follow.
This release adds new powerful analysis modules and time-saving capabilities to the ETAP suite. This brochure highlights key functionality in Release 7.0 of ETAP, which encompasses a broad and robust set of new features and enhancements.

Templates

One-Line Diagram
- Auto-Select
- Keyboard Shortcuts
- Symbol Library

Load Analyzer

Single-Phase Arc Flash

Arc Flash Analyzer

Switching Management

Libraries
- Solid State Trip Devices
- Cable
- Transmission Line
- Relay
- Battery


Modules
- Base Package
- Load Flow Analysis
- Arc Flash Analysis
- Transient Stability
- Harmonic Analysis
- Star Device Coordination / Selectivity
- Star Sequence-of-Operation
- Data Exchange

ETAP Real-Time
- Real-Time Server
- Advanced Monitoring
- Real-Time Simulation
- Automatic Generation Control
- Energy Accounting
- Load Forecasting
- Intelligent Load Shedding

ETAP 7.0 Brochure
ETАP Pоwer Stаtiоn, ETАP Enterprise Sоlution fоr Electricаl Pоwer Systеms

2009 07 latest crack software download

2009-07-31 ArtCAM v2009 SP2
2009-07-29 Reaction.Design.Chemkin.Pro.v15083 for Linux &Win
2009-07-28 AUTODESK.SHOWCASE.PROFESSIONAL.2010.R1
2009-07-28 VERO_VISI-SERIES_V17 (c) VERO SOFTWARE
2009-07-27 Bentley.CulvertMaster.03.02.00.01
2009-07-26 ICAM.CAMPOST.v18
2009-07-24 Maplesoft.Maple.v13.01.UPDAT
2009-07-23 Vellum Xenon v8.841
2009-07-23 PamStamp.2G.V2008.0.2
2009-07-22 VSNI.GenStat.v12.1.0.3278
2009-07-21 Tecplot.RS.2009.R2.b5281
2009-07-20 WAsP.v9.1 WAsP.Map.Editor.v9.1
2009-07-19 Etap.PowerStation.v6.0
2009-07-19 Leica.Cyclone.v6.0.4
2009-07-18 CSI Column v8.4.0
2009-07-15 TracePro 5.0.4
2009-07-15 DHI.MIKEZero 2009
2009-07-13 Csi.Etabs.StandAlone.V9.6
2009-07-11 Numeca.Fine.V8.7.2
2009-07-10 DELCAM POWERMILL V10
2009-07-09 Siemens.SIMATIC.S7.PLCSIM.v5.4.SP3
2009-07-07 AUTODESK.MOLDFLOW.V2010
2009-07-05 Siemens.Simatic.Step7.Professional.Edition.2006.SR6
2009-07-04 PTC.PRO.ENGINEER.WILDFIRE.V4.M092.Win32&WIN64
2009-07-04 GIBBSCAM.2009.V9.3.9
2009-07-03 Nemetschek Allplan 2009 Multilingual Retail
2009-07-03 WaveMetrics.IGOR.Pro.v6.1.0.Incl.Keymaker
2009-07-02 Solidworks 2009 with sp4
2009-07-02 SOLIDCAM 2009
2009-07-01 Autodesk.Navisworks.Review.2010.Multilangual
FROM caxcrack
2009-07-30 ARM SOC DESIGNER 7.1
2009-07-29 CoWare.Processor.Designer.V2009.1
2009-07-29 CoWare.Signal.Processing.Designer.v2009.1
2009-07-27 Cadence CONFRML V8.1
2009-07-24 Mentor.Graphics.PADS.Flow.9.0.1
2009-07-24 Novas 2009.07
2009-07-23 Mentor Graphics Precision Synthesis v2009a
2009-07-22 Simucad 2009
2009-07-19 HDL.Works.HDL.Design.Entry.EASE.v7.2.R8
2009-07-18 AWR.Design.Environment.v8.06
2009-07-16 Synopsys TetraMax 2008.09 SP5
2009-07-15 Magma FineSimPro 2008.09
2009-07-14 Synopsys.Sold.v2009.4
2009-07-13 Cadence LDV v5.16
2009-07-12 Cadence_IC v6.13
2009-07-11 Aldec.ALINT.2009.02
2009-07-10 Agilent.Genomic.Workbench.v5.0.14
2009-07-01 SpeedXP Suite V8.0
2009-06-30 MikroBasic Pro AVR 2009 v1.50
2009-06-30 MikroBasic Pro PIC 2009 v2.15
2009-06-28 Aldec.ALINT.2009.02
2009-06-25 Laker 32v4 P2
2009-06-23 Verdi v2009.04
2009-06-22 Altium Designer Winter 09 Build 8.3.0.16776
2009-06-20 Cadence.CTS v9.1
2009-06-19 Cadence TSI v6.1
2009-06-18 Tanner Tools V14
2009-06-15 LAker 32v3p6 LINUX
2009-06-12 Mentor Graphics HyperLynx 2009
2009-06-11 Agilent.SystemVue.v2009.05
2009-06-09 Mentor Graphics PADS 9.0 updata1
2009-06-08 Cadence SPB 16.2 Linux
2009-06-07 Mentor Graphics EE2007.5 with update2 Linux