Laker-v3.2-v1p5 (c)Silicon Canvas

Major Benefits

Cuts layout time in half while sustaining important aspects of handcrafted layout density
Total system allows user to create layout from floor planning, device creation, placement, wire connection, to layout verification and correction without the need for data translation
Supports latest process design rules to meet the physical implementation requirements of Ultra-Deep-Submicron (UDSM) and Design-For-Manufacturing (DFM)
Fully customizable bind keys to increase individual productivity and reduce the learning curve for new users
Device-level manipulation reduces tedious/error-prone layout creation and editing.
Shape and Grid Based routers for both full custom and cell-based design applications
Download foundry-certified Laker technology files to instantly use the plug-and-play Laker solution
Schematic-Driven Layout Flow works efficiently with legacy and new designs



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Major Features

Integration Capability
Versatile System:
Import designs from EDIF, Spice netlist, or work with Laker-AMS to perform Schematic-Driven Layout flow.
Integration with 3rd party physical verification solutions:
Tight link with Mentor Graphics Calibre and Synopsys Hercules for DRC/LVS. Run Calibre or Hercules on one block or the whole chip directly from the Laker menu.

Layout Planning
Custom Floor Planner:
Supports block area estimation with reshaped aspect ratio. Assigns pin locations automatically and
provides congestion map information to offer best-practice floor planning scheme. Mixes Soft and Hard Instances to minimize the gap between top-down planning and bottom-up layout realization.
Stick Diagram Compiler:
Provides a higher level of abstraction enabling more efficient transistor floorplanning, such as gate
merging, swapping and splitting.
Automatic Transistor Placer:
Optimum transistor placement achieved automatically through chaining, folding, and connectivity-based placement.
Matching Creator:
Customize transistor symmetry using a high level abstraction matching table. Quickly realize transistor placement according to user-defined matching patterns.

Advanced Device Model
Magic Cell (MCell):
Built-in UDSM DRC-correct device generator. Provides flexible device models thus enabling
extremely efficient creation of the devices physical layout from circuit components of a netlist or schematic. Magic Cell reduces the effort for device preparation and provides higher levels of device manipulation. Most importantly, Magic Cell is the only device model that has the ability to deliver handcrafted quality and guarantee zero DRC violations.

Built-in Shape and Grid Based Router
Net Router:
Automatically route single or multiple nets, DRC and LVS clean.
Point to Point Router:
Click on source and target to automatically create a DRC clean route. Or use it in an interactive mode while routing between source and target. Interactive settings for each layer include (1) availability for routing, (2) horizontal and vertical cost functions, and (3) width and space.
Pathfinder:
Interactive single layer DRC-correct path creator. Router follows the mouse in a point and click mode, recognizing same layers and routing around them. Use bind keys to switch between routing layers.
Route by Label:
Using text, or labels, as a guide, routes are automatically created between multiple points.

Hierarchy Manipulation Capability
Manipulate circuit hierarchy on Design Browser or Layout Window in order to optimize layout.

Pattern Recognition Technology
Copy & Associate:
Automatically comb through design database to find matches for selected items. Then automatically copy physical layouts and assign correct connectivity. Drastically reduce time spent on building repeat circuitry.
Pattern Reuse:
Automatically comb through design database to find matches for cells where the hierarchy of the physical layout does not match that of the original schematic. Copy patterns and create new layouts with correct connectivity. Drastically reduce time spent on building repeat circuitry.

Correct-by-Construction
Rule-Driven Editing:
While editing polygons, automatically check, display, and snap to width, space, notch, overlap, and enclosure rules. Increases productivity by reducing need to use
rulers and look up design rules.
Flight Lines & Real-Time Short Detector:
Flight Lines guide user on where to wire. Real-Time short detector displays short errors as
they are created. Both are used to ensure LVS-correct layout results.
Push Wire:
Create a path where you want, push-wire will move same layer routes out of the way.

ECO Capability
Laker compares an ECO netlist with the existing layout and then displays physical and/or logical discrepancies in the Design Browser window. Use automated functions to fix the discrepancies and match the layout back to the schematic.

Layout Debugging and Correction
Auto DRC Correction:
Fix DRC violations automatically, based on user selected area or Laker DRC error viewer. All fixed layout results will keep original connections, so as not to introduce additional LVS violations. Supports Laker-iDRC, Calibre, and Hercules DRC verification tool error reports.
Hierarchical Net Tracer:
Provides a unique feature to trace physical net connectivity through any/all levels of hierarchy.
Verification Explorer:
Seamless integration with third-party industry standard layout verification tools allows the user to browse and debug DRC errors