Mentor-Graphics-FPGA-Advantage V7.3

FPGA Advantage is a complete Integrated Design Environment (IDE)
targeting high-complexity FPGA device design. The FPGA Advantage IDE
spans the RTL FPGA design flow featuring advanced design entry,
verification, synthesis and implementation sub-flows. FPGA Advantage
accelerates total product design with integration of FPGA IO design
as well as bi-directional integration of the PCB design flow. This
latest release extends the FPGA Advantage IDE to include:
- Improved integration with Precision Synthesis
- Increased "ease of use"
- Extended synthesis device support

Language Independence.
The only unified flow that lets you design for

Any Silicon:
PLD, FPGA, Platform FPGA, Structured ASIC, ASIC Prototypes, ASICs and SOCs
Any Vendor:
Actel, Altera, Atmel, ChipExpress, Lattice, Xilinx, plus any ASIC foundry
Any Language:
VHDL, Verilog, SystemVerilog, C/C++, PSL, SVA

Delivering the technical edge

Maximize QoR, Fmax and area utilization on every leading FPGA platform
Optimize FPGA timing closure with Precision Synthesis and advanced timing analysis
Optimize system timing closure with I/O optimization & PCB integration
Fastest, standards based, multi-lingual simulation platform available

Optimizing your design process

Cut design time in half: Rapid design development process
Practical reuse: RTL reuse methodology
Team productivity: Team design flow and version management
Tune your competitive edge: Flow management and customization
Cut lab time with: FPGA-centric analysis and debug

Optisystem-V6.0

The latest version of OptiSystem features a number of requested enhancements to address the design of passive optic network (PON) based FTTx, optical wireless communication (OWC), and radio over fiber systems (ROF).

Comprehensive Multimode Library

The Multimode Component Library of OptiSystem 6.0 includes an exciting new feature empowering users with the option to load multimode fibers measurements of modal delays and power-coupling coefficients using the Cambridge file format. As result, users now can calculate the MMF link frequency responses faster allowing extensive statistical modeling of multimode-fiber links.

Sophisticated Amplifier Library

Design a variety of waveguide and fiber optic amplifiers using OptiSystem. Determine the tradeoffs between EDFAs, EYDFs, EYDWs, YDFs, SOAs and Raman amplifiers cost and performance. OptiSystem 6.0 automates the analysis of laser pulses by plotting autocorrelation and FROG (Frequency Resolved Optical Gating) graphs directly from the optical time domain analyzer.

New Component Libraries

Bidirectional Optical Fibers: A new discretization parameter for broadband sampled signals offers improved performance, accuracy, and convergence for doped amplifier gain and Brillouin calculations.

Wideband Traveling Wave SOA: Flexible selection between a static or dynamic model.

AWG NxN Bidirectional: A sophisticated new AWG model facilitates the design of AWG based PON using the unique bidirectional capabilities of OptiSystem.

Optical Sources: VCSEL Laser and Laser Rate Equations: A new adaptive step engine allows for fast convergence of high frequency analog signals.

CATV Carrier Generators: New parameters include the ability to enable or disable specific channels, facilitating the measurements of carrier to noise ratio (CNR).

Carrier Generator Measured: A new list of pre-defined set of standard carrier spacing allows for easy setting up of PAL GB (up to 97 channels), NTSC (up to 157 channels) and L (up to 58 channels) systems.



Microwave components

180 and 90 Degree Hybrid Couplers, DC blockers, power splitters and combiners: A new component library geared for ROF applications. Applications include mixers, power combiners, dividers, modulators, and phased array radar antenna systems. Control amplitude and phase balance of different components.

Measured components: Bidirectional S-parameters components allow users to load s1p, s2p, s3p and s4p file formats, including s2p with noise figure data.

Passives

Polarization Delay and Phase Shift components: New components which control the delay and phase shift for each polarization. Control the delay calculation, by using linear or discrete delay.

Periodic Optical Filter: A new multi-band optical filter with user defined transmission function.

Regenerators

MLSE (maximum likelihood sequence estimate) Electronic Equalizer: Introducing an advanced component feature using the Viterbi algorithm to equalize the input signal through a dispersive channel.

Free Space Optics

OWC (Optical Wireless Communication) Channel: A subsystem of two telescopes and the optical wireless channel between them facilitating the simulation of intersatellite communication links. FSO is a telecommunication technology that uses light propagating in free space to transmit data between two points. The technology is useful where the physical connection of the transmit and receive locations is difficult, for example in cities where the laying of fiber optic cables is expensive.

Laker-v3.2-v1p5 (c)Silicon Canvas

Major Benefits

Cuts layout time in half while sustaining important aspects of handcrafted layout density
Total system allows user to create layout from floor planning, device creation, placement, wire connection, to layout verification and correction without the need for data translation
Supports latest process design rules to meet the physical implementation requirements of Ultra-Deep-Submicron (UDSM) and Design-For-Manufacturing (DFM)
Fully customizable bind keys to increase individual productivity and reduce the learning curve for new users
Device-level manipulation reduces tedious/error-prone layout creation and editing.
Shape and Grid Based routers for both full custom and cell-based design applications
Download foundry-certified Laker technology files to instantly use the plug-and-play Laker solution
Schematic-Driven Layout Flow works efficiently with legacy and new designs



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Major Features

Integration Capability
Versatile System:
Import designs from EDIF, Spice netlist, or work with Laker-AMS to perform Schematic-Driven Layout flow.
Integration with 3rd party physical verification solutions:
Tight link with Mentor Graphics Calibre and Synopsys Hercules for DRC/LVS. Run Calibre or Hercules on one block or the whole chip directly from the Laker menu.

Layout Planning
Custom Floor Planner:
Supports block area estimation with reshaped aspect ratio. Assigns pin locations automatically and
provides congestion map information to offer best-practice floor planning scheme. Mixes Soft and Hard Instances to minimize the gap between top-down planning and bottom-up layout realization.
Stick Diagram Compiler:
Provides a higher level of abstraction enabling more efficient transistor floorplanning, such as gate
merging, swapping and splitting.
Automatic Transistor Placer:
Optimum transistor placement achieved automatically through chaining, folding, and connectivity-based placement.
Matching Creator:
Customize transistor symmetry using a high level abstraction matching table. Quickly realize transistor placement according to user-defined matching patterns.

Advanced Device Model
Magic Cell (MCell):
Built-in UDSM DRC-correct device generator. Provides flexible device models thus enabling
extremely efficient creation of the devices physical layout from circuit components of a netlist or schematic. Magic Cell reduces the effort for device preparation and provides higher levels of device manipulation. Most importantly, Magic Cell is the only device model that has the ability to deliver handcrafted quality and guarantee zero DRC violations.

Built-in Shape and Grid Based Router
Net Router:
Automatically route single or multiple nets, DRC and LVS clean.
Point to Point Router:
Click on source and target to automatically create a DRC clean route. Or use it in an interactive mode while routing between source and target. Interactive settings for each layer include (1) availability for routing, (2) horizontal and vertical cost functions, and (3) width and space.
Pathfinder:
Interactive single layer DRC-correct path creator. Router follows the mouse in a point and click mode, recognizing same layers and routing around them. Use bind keys to switch between routing layers.
Route by Label:
Using text, or labels, as a guide, routes are automatically created between multiple points.

Hierarchy Manipulation Capability
Manipulate circuit hierarchy on Design Browser or Layout Window in order to optimize layout.

Pattern Recognition Technology
Copy & Associate:
Automatically comb through design database to find matches for selected items. Then automatically copy physical layouts and assign correct connectivity. Drastically reduce time spent on building repeat circuitry.
Pattern Reuse:
Automatically comb through design database to find matches for cells where the hierarchy of the physical layout does not match that of the original schematic. Copy patterns and create new layouts with correct connectivity. Drastically reduce time spent on building repeat circuitry.

Correct-by-Construction
Rule-Driven Editing:
While editing polygons, automatically check, display, and snap to width, space, notch, overlap, and enclosure rules. Increases productivity by reducing need to use
rulers and look up design rules.
Flight Lines & Real-Time Short Detector:
Flight Lines guide user on where to wire. Real-Time short detector displays short errors as
they are created. Both are used to ensure LVS-correct layout results.
Push Wire:
Create a path where you want, push-wire will move same layer routes out of the way.

ECO Capability
Laker compares an ECO netlist with the existing layout and then displays physical and/or logical discrepancies in the Design Browser window. Use automated functions to fix the discrepancies and match the layout back to the schematic.

Layout Debugging and Correction
Auto DRC Correction:
Fix DRC violations automatically, based on user selected area or Laker DRC error viewer. All fixed layout results will keep original connections, so as not to introduce additional LVS violations. Supports Laker-iDRC, Calibre, and Hercules DRC verification tool error reports.
Hierarchical Net Tracer:
Provides a unique feature to trace physical net connectivity through any/all levels of hierarchy.
Verification Explorer:
Seamless integration with third-party industry standard layout verification tools allows the user to browse and debug DRC errors

Magma.blast.v5.0

Magma provides leading software for designing highly complex integrated circuits while maximizing Quality of Results with respect to area, timing and power, and at the same time reducing overall design cycles and costs. Magma provides a complete RTL-to-GDSII design flow that includes prototyping, synthesis, place & route, and signal and power integrity chip design capabilities in a single executable, offering "The Fastest Path from RTL to Silicon"? Magma's software also includes products for advanced physical synthesis and architecture development tools for programmable logic devices (PLDs); capacitance extraction; and characterization and modeling. The company's stock trades on Nasdaq under the ticker symbol LAVA.
The Magma hierarchical design flow includes Blast Fusion for block and top-level physical implementation and Blast Plan Pro for design planning and prototyping. Blast Plan Pro includes three key capabilities in the flow, comprehensive floorplanning, an automated early design planning and prototyping methodology and gate-level partitioning.

Blast Plan Pro抯 comprehensive floorplanning includes IO pad placement, interactive partitioning, soft-block placement and shaping, global-router-driven pin placement and optimization, industry-leading hard macro placement, time budgeting, hand routing for analog or power nets, and automatic power routing with a pushdown capability.

Blast Plan Pro provides a black box methodology for automated early design planning and prototyping.With this methodology, design teams can employ a top-down design approach where the design is floorplanned, partitioned, time budgeted, prototyped and fully implemented at the chip level with Blast Fusion well before block-level RTL is finalized. This methodology can ensure the shortest possible time to market by allowing the designer to start planning and implementing very early in the design cycle and by eliminating the top-level surprises, such as not meeting timing or not being able to successfully route the design, that can often arise late in the design cycle.

Blast Plan Pro抯 fast, high-capacity, gate-level partitioning and prototyping uses a virtually flat, timing-driven placement and partitioning technique that allows designers to perform extensive what-if analysis and quickly and accurately assess the feasibility of their design with respect to timing, physical implementation and electrical effects. Input netlist quality, timing constraints and floorplan alternatives can be quickly analyzed and validated resulting in design problems being found and fixed earlier in the design flow, preventing costly back-end iterations, providing higher confidence that design closure can be achieved, and potentially reducing manufacturing costs by allowing the designer to quickly evaluate floorplans with different aspect ratios and sizes. At any stage in the Magma hierarchical design flow, a design may consist of some mix of gates, RTL, hard macros, black box models, implemented blocks in the form of GlassBox models and implemented blocks in full detail. Blast Plan Pro seamlessly handles this mix of model types and model detail and provides for continuous updating and rebudgeting of top-level timing as blocks in the design progress through the design process until completed.

Key Capabilities in Blast Plan Pro
A successful hierarchical design flow requires a number key technologies and capabilities. Blast Plan Pro fullfills this requirement with its easy to-use GUI, accurate and memory-efficient modeling for hierarchical blocks, high-quality macro placement, partitioning, pin optimization and time budgeting, and support for feed-throughs and top-level routing tunnels.

ZUKEN-CadStar- v10.0

Zuken announces the latest version of the desktop PCB design solution, CADSTAR 10.0, which includes the addition of a large number of intelligent functionalities for schematic, library and PCB design, tighter integration with FPGA design tools, and the introduction of an alternative schematic front-end solution E³.logic.

Design Control
There has been an increased focus on supporting both the engineer and designer to create “right-first-time” designs in shorter time frames. CADSTAR offers users the ability to perform version control at the parts and component level, store parts information in the PCB design, set-up detailed layer stacks for buried and blind via technologies and carry-out impedance controlled routing. CADSTAR 10.0 also includes extended ODB++ output for manufacturing, the ability to highlight nets using multiple colors, plus FPGA design integration and a fully integrated parts library manager in ‘Design Editor’.

Ease-of-use
Ease-of-use with the well-known intuitive workflow has been further improved, to include integration of additional features for assigning any combination of function keys, enhanced layers settings GUI, support of custom colors using the standard Microsoft color dialog, smart update of new software releases and automatic parts index creation. All interactive operations are available while working in a mirrored view in the intelligent place & routing tool, P.R.Editor, for intelligent interactive lengthening or re-lengthening.

E³.logic for CADSTAR
Zuken’s E³.series module, E³.logic, can now be offered as an add-on solution for CADSTAR to further boost users’ productivity. Used as a front-end solution for CADSTAR PCB design it will allow support of multilingual diagrams, multilingual text and Unicode. The use of the E³.Logic database as a back-end solution for CADSTAR PCB design reduces the time spent searching for existing parts, integrates easily with specific MRP, ERP or PDM systems and works with databases that comply with Microsoft's ODBC standard. The CADSTAR E³.logic integration also provides opportunities to directly integrate with other E³.series modules such as E³.cable for complete system level integrated electronics and electrical design.

FPGA Integration
The recently introduced add-on module, CADSTAR FPGA, supports one universal project manager that controls all the design files for simulation, synthesis, place and route and pin assignment to the PCB board, as well as the I/O synchronization between the FPGA device and the PCB board.
This will allow the FPGA designer to forward and backward annotate pin swaps with the PCB layout.

LightTools-v6.0 With SR2

LightTools 6.0 Delivers Expanded Modeling and Optimization Capabilities

LightTools® 6.0, a major new release of the leading illumination design and analysis software from Optical Research Associates (ORA®), delivers an even broader set of system modeling tools and further improves its unique and powerful optimization capabilities. For example, LightTools now includes a user-defined optical properties feature that provides tremendous flexibility in creating specialty optical components. This allows modeling of application-specific, proprietary elements such as specialty polarization components, grating components (with efficiency calculations), scattering surfaces (including anamorphic scatterers) and coating definitions. In addition, LightTools 6.0 allows modeled elements to be immersed in one another in multiple levels – a capability needed for modeling the embedded phosphor and epoxy covering in an encapsulated LED, for example.

The LightTools optimization module, available in beta form in previous LightTools releases, has already proven to be a widely applicable feature that can automatically find optimal illumination design solutions, saving the designer days or even weeks of effort that might be needed to manually explore the design space. LightTools 6.0 brings the first formal release of the optimizer and expands it in several important ways. In particular, it now permits optimization of a given illumination distribution (e.g., uniform or Gaussian) while simultaneously maximizing optical power. LightTools also adds functionality for evaluating how sensitive a system is to variations in specific parameters. This can be useful for selecting variables before beginning optimization, and even enables some basic tolerance analysis computations.

Cadence-MMSIM-V6.2 For LinUx86 &Win

Cadence Design Systems, Inc. (NASDAQ: CDNS), the leader in global electronic-design innovation, unveiled Cadence(R) Virtuoso(R) Multi-Mode Simulation (release MMSIM 6.2), the electronic design industry's first end-to-end simulation and verification solution for custom IC that uses a common, fully integrated database of netlists and models to simulate analog, RF, memory, and mixed-signal designs and design blocks. This breakthrough allows designers to switch from one simulation engine to another without compatibility issues or interpretation impacts, so consistency, accuracy, and design coverage are improved, while cycle time and risk are reduced. The overall result is lower cost of adoption, support, and ownership, and faster time to market.

Virtuoso Multi-Mode Simulation is tightly integrated with the new Virtuoso custom design environment, enabling a complete design-to-verification methodology. In addition, Virtuoso Multi-Mode Simulation provides an innovative and cost-efficient token-based licensing model that allows designers to optimize their usage of different simulation technologies. This model significantly reduces the adoption and support costs typically associated with using multiple simulation technologies from different vendors.

"IBM Global Engineering Solutions deals with a broad range of designs every day, from high-end foundry devices to memories, SERDES, standard cells, I/Os, cores and microprocessors. We regularly use Virtuoso Spectre Circuit Simulator, Virtuoso Spectre XL for RF design, Virtuoso UltraSim and Virtuoso AMS Designer simulators for circuit simulation, RF analysis, and full chip mixed signal verification," said Mark Merrill, Director of IBM Silicon Solutions Engineering and IP Development. "Cadence Multi-Mode Simulation, based on common technology and infrastructure, has provided our designers with a reliable verification solution improving productivity and reducing support costs."

"National Semiconductor uses the complete Cadence Virtuoso Multi-Mode Simulation components, so we see immediate benefits to having an integrated, easy-to-choose simulation model," said Bill Meier, Senior CAD Manager of National Semiconductor. "This solution has enabled thorough verification throughout the design cycle of our leading edge analog products like power management, data converters, and communications interfaces."

"The ground-breaking Cadence Virtuoso Multi-Mode Simulation enables verification throughout the design cycle, across design teams, and even across device types," said Charlie Giorgetti, corporate vice president of marketing for Virtuoso and Allegro Platforms at Cadence. "Customers demand front-to-back design solutions for advanced design. Virtuoso Multi-Mode Simulation addresses design verification challenges for the entire spectrum of custom IC designs at various design domains while being tightly integrated with the new Virtuoso custom design environment, enabling a complete design-to-verification methodology."

Virtuoso Multi-Mode Simulation Supports Kits
The new Virtuoso Multi-Mode Simulation supports the recently released Cadence AMS Methodology Kit, RF Design Methodology Kit, and Low Power Methodology Kit. All three kits offer advanced methodologies and best practices using, among other things, Cadence Virtuoso Multi-Mode Simulation for verification.

What's New in Virtuoso MMSIM 6.2—Tiered Enhancements
Virtuoso MMSIM 6.2 provides a holistic, integrated simulation solution and shared licensing model that better meet diverse customer needs. This solution includes Virtuoso Spectre Circuit Simulator, Virtuoso UltraSim Full Chip Simulator, and Virtuoso AMS Designer. Each of these simulators includes tiered configurations with enhancements tailored to specific levels of design complexity. All are tightly integrated into the Virtuoso Platform Analog Design Environment.

Cadence Virtuoso Spectre Circuit Simulator L

Fast, accurate SPICE-level simulation; optimized engine provides up to 3x performance improvement over traditional SPICE tools
Enhanced Monte Carlo analysis reduces simulations by a factor of up to 10x
Virtuoso Spectre Circuit Simulator XL

Integrated analog, RF and high-speed IC simulation capabilities
Enhanced frequency-domain mutli-rate harmonic balance engine for fast, accurate simulation of high dynamic range, weakly non-linear RF circuits
Patented time-domain shooting algorithm optimized for highly non-linear circuits
New flow for analysis of analog noise and jitter analysis in phase-locked loops, the root cause of silicon re-spins in many mixed-signal SoC designs
Virtuoso UltraSim Full-Chip Simulator L

Fast, high-capacity, SPICE-accurate transistor-level simulation for pre- and post-layout verification at block- and full-chip level for analog, mixed-signal, RF, memory and SoC designs
Virtuoso UltraSim Full-Chip Simulator XL

High-performance digital solver for fast verification of multi-million-transistor custom digital designs with up to 10X better performance
Easy-to-use flow for electromigration and IR drop analysis supports electrical verification of memories and large analog/mixed signal designs
Virtuoso AMS Designer

Mixed-signal simulation with easy access to Virtuoso Spectre L, Virtuoso Spectre XL, Virtuoso UltraSim L and Virtuoso UltraSim XL when needed
Enhanced mixed-signal RF with integration to Virtuoso Spectre XL
Significant performance improvements when used with Virtuoso UltraSim XL for SoC verification

Cadence-ASSURA- V3.17 for Linux

Assura™ Design Rule Checker (DRC) is part of the design verification suite of tools within the Virtuoso® custom design platform. Assura DRC is a full-featured tool that supports both interactive and batch operation modes and utilizes hierarchical processing for fast, efficient identification and correction of design rule errors in even the most advanced designs.

Key benefits

Simplifies design process with a common database for data transfer within the Virtuoso custom design platform
Accelerates design-to-volume with production-proven interactive design rule checking
Reduces re-spins by eliminating design rule errors before tapeout
Ensures fast, silicon-accurate custom design with an integrated silicon verification and analysis flow within the Virtuoso custom design platform


Assura™ Layout vs. Schematic (LVS) Verifier is part of the design verification suite of tools within the Virtuoso® custom design platform. Assura LVS ensures that the layout connectivity of the physical design matches the logical design represented by the schematic or netlist before tapeout by automatically extracting devices and nets formed across layout hierarchy and comparing them to the schematic netlist. Assura LVS provides fast, efficient verification in both interactive and batch mode.

Key benefits

Simplifies design process with a common database for data transfer within the Virtuoso custom design platform
Accelerates design-to-volume with production-proven interactive LVS debugger
Reduces re-spins by eliminating connectivity and mismatch errors before tapeout
Ensures success in analog mixed-signal design with support of mixed netlist and special devices

SoC ENCOUNTER RTL-to-GDSII SYSTEM v7.1 (c) Cadence

Designers of today's SoCs must manage shrinking geometries, increasing design sizes, and growing complexity. As a result, the technical challenge has become how to account for the effects of interconnect across the entire chip—from the outset of the implementation cycle. Additonally, electronics makers need a design system that can deliver the highest quality of silicon (defined as timing, area, and power with wires) along with accurate verification, signal-integrity aware routing and the latest low-power design and yield capabilities, which are critical for advanced 65nm and 45 nm designs.

Cadence SoC Encounter system addresses these requirements within a system that combines RTL synthesis, silicon virtual prototyping, and automated floorplan synthesis, clock network synthesis, design for manufacturability and yield, mixed-signal support, and nanometer routing. Optimized to support 130nm to 45nm designs, it enables full-chip implementation in a single system. SoC Encounter allows engineers to synthesize to a flat virtual prototype implementation—including full-chip, routed wires—at the beginning of the design cycle. Engineers have an early, accurate view of whether the design will meet its targets and be physically realizable. They can then choose to either complete the final implementation or to revisit the RTL design phase. The SoC Encounter system also supports advanced timing closure and routing, as well as signoff analysis engines for final implementation.

SoC Encounter boosts the productivity of design teams, helping them to manage design complexity, and get products to market faster. The SoC Encounter system is available in L, XL, GXL offerings.

Key Benefits:
Combines RTL synthesis, silicon virtual prototype and full-chip implementation in a single, silicon-proven system to achieve timing closure on complex designs
Provides fast, accurate and flexible feasibility analysis—which combines an automated floorplan synthesis and ranking system that enables rapid exploration of the design space with handoff to the physical implementation flow—for a predictable path to design closure
Delivers huge productivity gains through a high-capacity, high-throughput and highly integrated solution that can handle 50M+ gate designs in 130nm process technologies or below
Supports multiple implementation styles with built-in fast power planning, relative floorplaning, and signal integrity analysis
Supports multiple methodologies for flip-chip implementation with automatic RDL routing and 45 degree support, thereby promoting the concurrent design of chip and package
Proivdes highly integrated and consistent process variation fixing with the SSTA solution (includes In-the-Die, Die-to-Die, and Random variation support, block-based and path-based modes, standardized statistical ECSM library models, and characterization support
Incorporates the latest yield and low-power design capabilities for advanced 65nm and 45nm designs

AUTOFORM-MASTER-V4.1.1

the new features and enhancements provide the following main benefits:

The release of version 4.1.1 supplements the June release of version 4.1 with important enhancements offering increased accuracy and efficiency. This new release significantly enhances the performance of the core solver and improves the accuracy of the results.

The newly introduced adaptive mesh de-refinement for higher accuracy has a substantial effect on the simulation results. The accurate simulation results, in particular the precise stress distribution, are important for accurate springback calculation. As a result, the users can rely on an accurate final validation of tool and process layout, including springback simulation and springback compensation – the challenging topics in the sheet metal forming industry.

Accurate Springback Calculation and Springback Compensation: AutoForm's new springback feature automatically modifies tooling surfaces based on a precise springback calculation. Die-face engineers can directly take into account springback results and compensate the appropriate tool geometry. The compensated tool geometry is automatically used as new input for rapid and accurate tooling validation. As a result, more reliable process layouts are realized during early planning phases -- as AutoForm springback compensation minimizes the risk of later, costly changes of tooling or processes due to springback effects.

Precise Geometry Modelling: Significant improvements in geometry modelling are achieved by introducing morphing technology. By modifying wall angles, unfolding part areas and performing in-plane modification of details, keeping the regions outside of the morphing untouched, the user can easily evaluate the best geometry model and optimize the process.

More Efficient Die Development Process: The die development process can be shortened considerably using the new substitution and offset skins provided by AutoForm 4.1.1 Even the original, imperfect surfaces can be substituted by a watertight skin early in the development process. Watertight skins are required for CAD solid design. As a result, solid die design can be started at an earlier stage. Moreover, an additional skin, offset by a large value, can be generated fully automatically. Such offset skins are required for the casting model's solid design. Consequently, the die castings can be launched earlier, reducing the lead time by several weeks.


Accurate Forming Forces: AutoForm 4.1.1 is able to calculate accurate forming forces. Knowing the exact forming force, the user can define the adequate press equipment required for reliable production, at an early stage of the development process.

Ptc-Cadds5i-r14.4

Powerful Design Graphics Capability
CADDS 5 Release 14 now offers the ability to design in a full 3D explicit shaded environment. This powerful tool enables new levels of productivity in design and visualization. It provides a better understanding of complex design scenarios that help to eliminate misunderstandings and interferences by visualizing a true representation.
Robust and Proven
CADDS 5 has a robust and proven software modeling capability across a wide range of industries and projects. This is complemented by integration with the Optegra Workgroup data management solution for control and security of data.
3D View Clipping and Zoning
The new shaded environment is complimented by the capability to clip 3D views to visualize only those items within, or crossing, the defined clip box. This greatly reduces the dataset the user has to manipulate when working with complex designs. Working in both part and assembly mode, clipping can be invoked on individual or multiple views with different clip extents in each view.
Hidden Line Removal (HLR)
When selecting the HLR dataset, marked entities may now be included or excluded from the process. Clipping now respects all three view planes and offers a ‘Within’ and ‘Crossing’ clip boundary selection to provide greater flexibility. Depending on the view, you can choose to include or exclude a particular entity for each view when multiple views have been selected. The ability to save and restore View States in the assembly environment helps ensure the correct view status is taken when updating an HLR view. The user is now informed if attempting to update the HLR with an incorrect View State.

PTC-Optegra-V8.0

Optegra the workgroup data management solution for CADDS
5i provides an open, distributed information environment that
helps manufacturers flexibly and transparently manage,
control, and distribute all types of CADDS 5i and other
non-CAD related product development information.

The unique Optegra architecture allows information consumers
- from engineering to IT to sales and marketing - to browse,
locate, and access any information from desktop PCs and
workstations.


No matter where the data or users reside, up-to-date information is
available - from initial concept to product retirement.

Engineers describe and understand designs in terms of assemblies,
bills-of-material and 3D product multi-user CADDS 5i Concurrent
Assembly environment. It allows designers to dynamically create, view
, and manipulate a single master product model, assess assembly
structures and 3D product views.

ICEM-Surf-V4.7 (C) PTC

ICEM Surf provides breakthrough technology enabling users to produce world-class aesthetic products in today's competitive, global markets. Acknowledged as the premier system for the creation and development of Class A surfaces, ICEM Surf bridges the demands of aesthetic designers and production engineers from visualisation right up to tool and die designers.

The flexibility of ICEM Surf results in high-quality surfaces required in today's design environment, while substantially reducing overall design time. Product development teams using ICEM Surf leave the traditional process behind. ICEM Surf's integrated solutions enable users to implement a new, more efficient method of product development called Virtual Modelling. Stylists and engineers work out design treatments dynamically on screen and immediately see the aesthetic, as well as the engineering, implications of their ideas.

ICEM Surf also has special functionality to painlessly handle the input of digitised physical models. Surface models can be reverse engineered from ordered or unordered (point clouds) digitised data in a fraction of the time compared to other systems. Special diagnostic tools guide the user to form the correct balance between surface smoothness and adherence to the digitised data.

ICEM Surf supports the direct modelling techniques that optimise the update cycles in design and engineering. After creating an initial shape, the user can concentrate on developing the shape through Direct Modelling, operating on surfaces or even directly on scans (point clouds). As the scans or surfaces are directly manipulated, all diagnostics like cross sections or split lines are dynamically updated. With ICEM Surf you always see what you get.

By using ICEM Surf's Global Modelling function, whole detailed models can be modified in total – interactively and dynamically – giving the aesthetic designers an interactive tool to work out a design solution. With the new Unified Modelling approach, you can model all different kinds of entities with the same functionality, without even thinking about their geometric nature. Engineering can adapt structural surfaces to the modified aesthetic surface effortlessly through ICEM Surf’s Feature Modelling function.

And with simultaneous real-time analysis, you can monitor reflection lines, curvature, or deviation from reference data dynamically as you manipulate surfaces. This approach results in unparalleled surface quality and enables designers to converge on production quality surfaces in a fraction of the time that other systems would require for the same task.

Last but not least, ICEM Surf also takes you into Virtual Reality. The rendering module provides advanced rendering functions and photo-realistic images that give the designer a realistic view of the model for presentations and design reviews. You may use stereo mode for 3D visualisation of your CAD model, and real-time renderer for continuous assessment of your modifications in a realistic environment, while continuing to model the geometry.

Based on these techniques, ICEM Surf is the tool of choice in the automotive, tool and die, and product design industries where aesthetic design concepts must be implemented in harmony with product functionality. ICEM Surf allows the designer to create and visualise ideas freely. But most importantly, it allows an interactive environment for the collaboration of the designer and the product engineer. Through a comprehensive set of direct and standard CAD interfaces, ICEM Surf fits easily into any CAD environment.

With ICEM Surf, your product development teams can combine artistic style and engineering performance while developing fully feasible, aesthetic designs faster and with higher quality than with any other CAD system on the market today!

So ICEM Surf will lead to more efficiency if it is used as the platform system for freeform surfacing in any existing CAD/CAM environment.

With ICEM Surf, product styling is no longer held hostage by its engineering!

CST-Studio-Suite-V2008

The electromagnetic simulation software CST STUDIO SUITE™ is the culmination of many years of research and development into the most efficient and accurate computational solutions to electromagnetic design. It comprises the following modules:

CST DESIGN ENVIRONMENT™
CST DESIGN ENVIRONMENT™ (CST DE) is the access point to the CST STUDIO SUITE™

CST MICROWAVE STUDIO®
CST MICROWAVE STUDIO® (CST MWS) is a specialist tool for the fast and accurate 3D EM simulation of high frequency problems. Along with a broad application range, CST MICROWAVE STUDIO® offers considerable product to market advantages: Shorter development cycles - Virtual prototyping before physical trials - Optimisation instead of experimentation.

CST DESIGN STUDIO™
CST DESIGN STUDIO™ (CST DS) provides a powerful design environment in which the results from diverse simulators can be combined and analysed.

CST EM STUDIO™
CST EM STUDIO™ (CST EMS) is an easy-to-use tool for the analysis and design of static and low frequency structures.

CST PARTICLE STUDIO™
CST PARTICLE STUDIO™ (CST PS) is a highly specialised tool for the fully consistent simulation of free moving charged particles as in electron guns, cathode ray tubes, ... .

Solvaco-TCAD-SCAD-SmartSpice-AMS-V 2007

Silvaco International, a leading vendor of commercial TCAD software, today announced that Lite-On Semiconductor Corporation (LSC), a leading manufacturer of image sensors and discrete power devices, has standardized on the Silvaco TCAD process and device simulation flow to develop its next generation power devices.

“We chose the Silvaco TCAD solution for its broad functionality, reliable performance, experienced , straightforward business model and the clear Stanford-based roadmap for the future”, said C.C. Chen, executive VP, Discrete and Analog Division, for LSC. “We were able to simulate our existing processes and devices using Silvaco TCAD software without re-calibrating our existing Stanford-based model coefficients.”

Silvaco provides advanced TCAD technologies based on the latest physical models for process and device simulation. Customers of Silvaco TCAD software create leading-edge MOS processes and devices, SOI, power devices, and optical semiconductors for sensors, display panels, LEDs and lasers. Customers are switching to Silvaco TCAD from other TCAD because they do not have to recalibrate their model coefficients, re-establish their process and device simulation flows developed over many years, or learn new software.

About Silvaco TCAD Tools

ATHENA Process Simulation Framework enables process and integration engineers to develop and optimize semiconductor manufacturing processes. ATHENA provides an easy to use, modular, and extensible platform for simulating ion implantation, diffusion, etching, deposition, lithography, oxidation, and silicidation of semiconductor materials. It replaces costly wafer experiments with simulations to deliver shorter development cycles and higher yields.

ATLAS Device Simulation Framework enables device technology engineers to simulate the electrical, optical, and thermal behavior of semiconductor devices. ATLAS provides a physics-based, easy to use, modular, and extensible platform to analyze DC, AC, and time domain responses for all semiconductor based technologies in 2 and 3 dimensions.

Virtual Wafer Fab is an integrated environment of TCAD software to automate and emulate physical wafer manufacturing. These integrated tools facilitate the input, execution, run-time optimization, and results processing of TCAD simulations into one flow managed through a common database.

November 0day softwares

2007-11-30 ALGOR.Designcheck.v21.0
2007-11-27 CNCKAD V8.5 (C)Metalix
2007-11-26 SmartDraw.2008.ISO
2007-11-25 Graphisoft.ArchiCAD.v11.Hotfix.1114.Upgrade.Only
2007-11-24 Adina V8.4.2
2007-11-23 Dynaform.5.6 (C)ETA
2007-11-22 GibbsCAM.2007.v8.7.6
2007-11-21 ESI.Procast.v2007
2007-11-20 SolidWorks 2008 Office Premium for 64 BIT
2007-11-19 Intel.Cluster.Toolkit.Compiler.Edition.v3.1.ISO
2007-11-18 Dassault.Systemes.Catia V5R18 Sp2 for win32&win64
2007-11-17 MSC.SimDesigner.for.Catia.v5R17.R2.WiNNT2K
2007-11-15 MSC.Patran.v2007.R1B.WiNNT2K
2007-11-12 RiB_Stratis_v11.3_GERMAN
2007-11-12 MSC.SIMOFFICE.R2.1
2007-11-11 CSI_ETABS_9.16_UPDATE
2007-11-11 CSI_SAP_2000_V11.07_UPDATE
2007-11-11 Pointwise.Gridgen.v16.0.R2.LINUX&MACOSX&win
2007-11-10 GibbsCAM.2007.v8.7
2007-11-09 CADVANCE.V12.32
2007-11-07 Imold 2007 v8 forSolidworks2008
2007-11-06 EMS-I_GMS_V6.0_DC20070807
2007-11-05 Macrovision_AdminStudio_v8.6_Enterprise_Edition
2007-11-05 Combit_Relationship_Manager_v2007_BiLiNGUAL
2007-11-04 CGTECH_VERICUT_V6.1.2
2007-11-03 Dassault .Systemes.Catia V5R17 Sp7 for win32&win64
2007-11-02 Telelogic.Rhapsody .v7.1 for Win &Linux
2007-11-02 AutoCAD.Civil3D.2008.GERMAN
2007-11-02 DesignCAD.3D.Max.v18
2007-11-01 Dassault.Systemes.Catia.P3.V5R18 with SP1

ESI-Visual-Environment-v3.0.1

Visual Environment is the first brick of the new environment for ESI Group’s leading
crash simulation software. Visual Environment has been built by merging ESI Group’s
former environment solution into EASi’s inherited technology. The embedded data
model offers a very versatile environment where new applications and interfaces can
easily be implemented.

Visual-Mesh is a complete meshing tool which supports CAD Import, 2D and 3D
Meshing and Editing features. Some of the features which work on ‘mesh only’ will be
available in Visual-Crash PAM context.

Visual-Crash PAM (VCP), which is one of the contexts in Visual-Environment,
provides PAM-CRASH users with fast iteration and rapid model revision process, from
data input to visualization for crashworthiness simulation and design. This environment
provides quick model browsing, advanced mesh editing capabilities and rapid graphical
assembly of system models. VCP allows graphical creation, modification and deletion
of contacts, materials, constraints, control cards and all crash entities. In VCP, you are
provided with tools for checking model quality and simulation parameters prior to
launching calculations with the Solver. Using these tools helps in correcting errors and
fine-tuning the model and simulation before submitting it to a solver, thus saving time
and resources.

Visual-Safe is a context in Visual-Environment, dedicated to Safety utilities. High
productivity tools such as advanced dummy positioning, seat morphing, belt fitting and
airbag folding are provided in this context.

Visual-Safe MAD (VSM) is a complete, efficient and productive CAE environment for
multi-body and finite element occupant safety simulations using Madymo. It utilizes the
multi-window/multi-model/multi-application environment of Visual-Environment
very efficiently. It provides complete flexibility of working for both the experienced
and the novice Madymo users alike. It incorporates a vast database of customer
requirements and feedback gathered over a decade.

Visual-Medysa guides PAM-MEDYSA 2G users in building system models for design
optimization and performance validation of complex mechanical systems. Mechanical
systems such as engine, tires, chassis, suspensions, and machinery transmissions, can be
modeled with ease in this environment.

High Velocity Impact (HVI) simulation is used to analyze the dynamic behavior of
materials under very high speed impacts. Visual-HVI supports PAM -SHOCK HVI
user in modeling such material data easily. This typically finds applications in
aerospace where we need to understand the damage suffered by a spacecraft when it
encounters space debris, such as micro-meteoroids.

Visual-Viewer is the new generation Post Processing tool with state-of-art Plotting
utility. This caters to the requirements of the CAE community. Visual-Viewer is built
on the multi page/multiplot environment, which enables the user to group his data into
pages and plots. Visual-Viewer is designed with intuitive and sleek user interface with
Windows look and feel. Complete session can be re-run without loss of any data.

Visual-Viewer is completely command driven which enables the user to execute
commands at ease. Visual-Viewer is completely built on multi-page and multi-plot
environment. The user has the freedom to create any number of pages and to have upto
16 windows in a single page. These windows can be plot, animation, video, model or
drawing block windows. The entire snapshot of the product can be saved as a template
and restored any time.

Visual-Process Executive’s Process-oriented philosophy brings a compelling
advantage to PAM-CRASH users to build processes quickly by customizing GUIs and
to execute them.

Visual-Crash Dyna (VCD) provides advanced capability and fast-guided model
building of LS-DYNA solver. Using Visual-Environment multi-window/multimodels/
multi-application environment, with visual verification, complete model
building activity can be performed efficiently.

Visual-Seal provides advanced capability and fast-guided model building of Seal
model. Using the Visual-Environment multi-window/multi-model/multi-application
environment, with visual verification, complete model-building activity can be
performed efficiently.

Visual-Life Nastran (VLN) is a comprehensive, integrated environment for Nastran
simulations with powerful enterprise capabilities. VLN is a ‘high-performance’
software to manage and assemble large and complex finite element system models for
Nastran, NVH and durability analysis with its unique multi-window / multi model
environment providing high productivity with powerful visualization and model
browsing.

Visual-Crash Rad (VCR) (Beta) provides advanced capability and fast-guided model
building of RADIOSS solver. Using Visual-Environment multi-window/multimodels/
multi-application environment, with visual verification, complete model
building activity can be performed efficiently.

FEKO-Distrib-V5.3

FEKO Suite 5.3
Major highlights include

* OPTIMISATION: Complete re-design and re-implementation of the optimisation process and workflow.
* NON-RADIATING NETWORK ANALYSIS: A general network implementation for the inclusion of multi-port S- Z- and Y- parameter-based networks.
* Geometrical Optics (GO): A new implementation for the analysis of electrically large dielectric bodies e.g. dielectric lens antenna.

User Interface

* Stand-alone command-line driven tool for CAD model re-evaluation and meshing.
* POSTFEKO GUI available on the 64-bit x86_64 platform.
* Selective importing from existing CADFEKO models.
* GID mesh import.

Kernel

* Geometrical Optics for dielectrics: A new method is available for the analysis of large dielectric structures, particularly for lens antenna applications.
* General non-radiating networks: Multiple cascaded general multiport networks (based on S- , Y- and Z- matrix representations) may be included in the FEKO model. Current interaction is taken into account at the network-geometry connection points.
* Fast near-field calculations for the MLFMM: Dramatic reduction in time required for computation of the near-field at many points for large models.
* Waveguide port excitation available on models that include dielectric parts: Available for MoM/SEP or FEM models or where the CFIE (combined field integral equation) is used on metallic objects.
* UTD extended: Provision for connection of multiple plates at a single edge.
* Support for the indexed point-arrays in EDITFEKO: Expansion to allow for point-array and variable-array based definition of polygon and polygonal plate geometry primitives in scripted geometry definitions with no limitation on the number of points used.

Improved parallel MLFMM efficiency: Run-time improvement due to load balancing and improved parallel communication schemes.
* Improved memory allocation on 32-bit Windows operating systems: The maximum memory allocation has been expanded by modification of the Windows DLL handling code.


Licencing

* Extension of the concept of a ”preferred” licence to node-locked licences.
*
Provision for the usage of a node-locked licence on a computer when network / nameserver access is not available: When a licence file containing mixed floating/node locked licences is used, network access is no longer required.

Synopsys.saber.v2007

Saber® software simulates physical effects in different engineering domains (hydraulic, electronic, mechanical, thermal, etc.) as well as signal-flow algorithms and software control. Saber is used in the automotive, aerospace, power and IC industries to simulate and analyze systems, sub-systems and components under a variety of different operational and environmental conditions. This dramatically improves design reliability while reducing the need for physical prototypes.

Key features include the industry's largest model library, advanced analyses (Monte Carlo, Stress, Sensitivity, etc.) to support Robust Design methodologies, integration into popular design environments, and support for standard modeling languages including MAST and VHDL-AMS. Saber improves design productivity while helping engineers create more robust, reliable and cost-efficient designs faster.

Wire harness design is the backbone of the electrical system for any vehicle, whether automotive, aerospace, or other form of transportation. Mission critical, safety, infotainment, etc. signals are carried through a complex network of wires and harness assemblies to every portion of the vehicle. Saber Harness was developed in partnership with leading automotive and truck manufacturers to ensure production-proven harness designs for the most demanding environments. Combined with the industry-standard Saber simulation tool suite, Saber Harness helps streamline costs, reduce design time, and ensures signal-carrying capacity for all components throughout the vehicle.

Industries

Automotive Automotive
The Saber design environment is the proven standard in automotive design groups worldwide. Automotive engineers rely on Saber's unique analysis capabilities to insure robust and reliable designs. With Saber, engineers are able to analyze the interactions between the complex hardware and software technologies used in modern automotive systems. Saber includes the ability to analyze performance sensitivities and stresses, investigate system failure modes, and evaluate a design's reliability and manufacturability all in the same environment. Automotive applications where Saber is successfully used include in-vehicle networking, powernet management, drive-by-wire control, powertrain, engine regulation, and many more. Production-proven with advanced capabilities, Saber is the top choice for Automotive engineers seeking the advantages of robust design and analysis.

Aerospace Aerospace
Flight-critical systems must operate accurately and reliably in extreme environments. Therefore, Aerospace engineers must consider and thoroughly analyze a variety of factors when designing aircraft systems. The Saber design environment is the preferred choice for Aerospace engineers seeking robust system analysis. Engineers can investigate environmental effects such as changes in atmospheric pressure, temperature swings, etc. They can also evaluate changes in system performance resulting from manufacturing tolerance spreads (stack up) in system components. Saber also allows engineers to inject failures in their designs to see how the rest of the system is affected. Aerospace applications where Saber is successfully used include fly-by-wire control, power network sizing and validation, radar and flight control computers, hydraulic power generation and distribution, and many others. Saber is the only tool that can deliver advanced analysis critical to the demanding safety and reliability requirements inherent in today’s Aerospace industry.

Cadence IC6.11 design for Linux

Personal consumer electronics and wireless products have become the dominant force in today's global electronics market. And relentless demand for new features and functionality in these devices is driving unprecedented growth in RF, analog, and mixed-signal applications. To create new products that fulfill this demand, IC designers must manipulate precise analog quantities—voltages, currents, charges, and continuous ratios of parameter values such as resistance and capacitance. This is when companies turn to custom design.

Full-custom design maximizes performance while minimizing area and power. However, it requires significant handcrafting by a select set of engineers with very high skill levels. In addition, custom analog circuits are more sensitive to physical effects, which are exacerbated at new, nanometer process nodes. To streamline the process of designing custom ICs and integrating them into end products, semiconductor and systems companies need sophisticated software and flow methodologies to meet time-to-market and time-to-volume goals. The Cadence Virtuoso custom design platform provides an exceptionally fast and silicon-accurate way to design custom analog, RF, and mixed-signal ICs.

Agilent.Genesys.v.2007.08

Agilent Technologies Inc. (NYSE: A) today announced the availability of GENESYS 2007, a new release of its popular RF and microwave design software in Agilent's Eagleware product line. The release includes improvements to simulation, tuning, optimization and integration through file-format export. The improvements help boost designers' confidence in circuit performance and speed the communications-design process.

"We're pleased to be shipping this high-performance and high-quality release," said Frank Vincze, product manager with Agilent's EEsof EDA division. "Early feedback from customers indicates we've hit the right balance of performance and technology that can cut development time and reduce or eliminate design turns."

Improvements and new features of Agilent's GENESYS 2007 release include:

* Improved performance: Faster and more accurate simulation, tuning and optimization
* New statistical yield analyses: Save and compare iterative results
* Improved intermediate file format (IFF) interface: Smoother export of GENESYS models into Agilent's industry-leading Advanced Design System (ADS) for more advanced simulations that get you closer to design implementation
* Expanded support for mixer spur tables in WhatIF: Use hardware-measured mixer models, with their range of frequency responses, to define operating frequencies
* Integrated ADS licensing: A common licensing protocol between GENESYS and ADS eliminates the need for a physical hardware key

GENESYS is an integrated and easy-to-use software suite with leading price performance for use in Windows PC environments. It supports a full range of communications design, from algorithms to artwork. GENESYS circuit-design software is used to develop products such as cellular telephones, radar systems, cable TV systems, satellite systems, mobile base-station equipment, Radio Frequency Identification (RFID) devices and wireless networking products. GENESYS also is used in high-frequency applications such as system-architecture design and analysis, linear simulation, non-linear and electromagnetic simulation, synthesis, and RF-board and microwave-IC layout.

Advanced-Design-System-(ADS)-V2008 (c)Agilent

Agilent Technologies Inc. (NYSE: A) today announced Advanced Design System release 2008. Advanced Design System (ADS) is an industry-leading high-frequency, high-speed electronic design automation (EDA) software platform. This release contains productivity breakthroughs for faster communications product design.

"Working closely with our top customers, we've enhanced this ADS release with user interface and technology improvements that speed the design process," said Jim McGillivary, general manager of Agilent's EEsof EDA division. "In 2008, I am challenging my development team to double customer productivity for a comprehensive set of typical design tasks, which we'll publish and track on our Web site."

Advanced Design System 2008's advanced, graphical user interface enhancements come from the same interface development platform used by the most popular Internet software tools and search engines, and contain advanced search and context-dependent features. The speed improvements gained from this new interface help make software-tools integration seamless for common and emerging design applications.

Speed and productivity enhancements include:

* improved project management, real-time zoom and pan, interactive 3-D layout viewing, stretching, and cut planes;
* improved LVS (layout vs. schematic) design synchronization, providing full control over the automation to guarantee the correct layout;
* updated design rule checking and fast, accurate artwork export/import for a smoother transition from design to production;
* full 3-D electromagnetic integration into ADS, for designers who increasingly need electromagnetic analysis for complete communications product design. The integrated Electromagnetic Design System also contains a faster bond wire drawing interface;
* the latest multi-processor computing, including support for today's 64-bit processors; and
* faster high-frequency Transient simulations, providing average speed improvements of up to 6x for large circuits.

Because high-speed digital designers are now facing the same physical design challenges that Agilent's EDA design tools have addressed for RF and microwave design, Advanced Design System 2008 features full support for high-speed, gigabit link (signal integrity) design, including advanced bit error rate measurement and analysis.

This is first in a series of four ADS releases expected in 2008. By the end of the year, Agilent plans to double productivity for common design and simulation tasks compared with previous versions of ADS.

OPTISWORKS-V2008 FOR SOLIDWORKS-2008 (C)OPTIS

• Simultaneously optimize optical and mechanical parts thanks to powerful optimization engine

• Import all optical systems created with traditional software

• Study tolerancing of your system thanks to multi-configuration capabilities

• Treat optical rays as 3D sketches

• Access a full set of optical components libraries

• Calculate all optical performances of your system (MTF, PSF, Spot diagrams, Aberrations…)

• Reduce system size thanks to free shape lens design & optimization
New functionalities
Virtual Human Vision Lab: Visual acuity, Condition of observation of the scene and Vision mode evaluation.

Virtual Human Vision Lab: Analysis tools.

Virtual Human Vision Lab: Legibility/Visibility tools.

ANSI/IESNA LM-63-2002 standard support.

ANSI/IESNA LM-63 Type A standard support.

Virtual Photometric Lab: Following operations on maps are now multithreaded: Open, Standard filtering, Remove highest peaks filtering, Map addition and multiplication by a value (Photometric Calc and Distributed calculation), Surface/Section calculations and Display update.

New OPTIS License Manager.

Virtual Photometric Lab: The export of spectral map to convert it into an extended map has been added.

Advanced Scattering Surface: The Autofill tool has been added to help the Advanced scattering generation.

Improvements
Availability of preferences from independent Labs: Virtual Photometric Lab, Virtual Human Vision Lab, User Material Editor, Spectrum Editor, Advanced Scattering Surface Editor and BSDF - BRDF - Anisotropic Surfaces Viewer.

IES / Eulumdat / Optis Intensity viewers: Horizontal symmetry and intensity's export to a Virtual Photometric map.

IESNA viewer: Graphic user interface for "Miscellaneous".

Sollner curve and Luminance calculation only available for IES C format.

Eulumdat viewer: Possibility to add symmetry properties on an existing intensity diagram (CAS-01655-1BEXMM).

Virtual Human Vision Lab: New Time adaptation dialog box.

Virtual Photometric Lab: Eye Illuminance.

Virtual Photometric Lab: Colorimetric data - Possibility to select a reference color and to calculate the DeltaE between the reference color and the selected color.

Rebuilt of the "Complete Scattering" model.

"Measure Treatment" feature added to the "BSDF - BRDF - Anisotropic Surfaces Viewer" to allow post-treatment of measured files.

Fixed bugs
Virtual Photometric Lab: BMP mask import has been fixed (CAS-01573-49SKT9).

Virtual Photometric Lab: The "Remove highest peaks" filtering has been corrected for radiometric values (CAS-01647-ZNBTWK).

Virtual Photometric Lab: The crash with grid parameters has been solved.

Virtual Photometric Lab: The crash when a not well written CLS file has been chosen as been solved.

Virtual Photometric Lab: The txt Import/Export command for a conoscopic map has been solved.

Virtual Photometric Lab: Saved of values for points' position of the "user line" of a conoscopic map has been solved.

Virtual Photometric Lab: The flux value when using Foot Candle has been solved (CAS-01913-AYLLNF).

When opening a Virtual Photometric Lab, the default filter with highest peaks remove has been solved.

User Material Editor: Units of the spectrum editor for fluorescence materials' absorption has been fixed (CAS-01548-DW70C2).

User Material Editor: It is not more possible to enter an index below than 1.0.

User Material Editor: A problem when displaying the index graph with very low variation of the index has been fixed.

Ray File Editor: The "Save As" command has been fixed (CAS-01929-X4J8HA).

Lambda minimum limitation for Spectrum Generation has been solved.

IESNA LM-63 Type B: The measured flux has been solved.



• Limit number of optical elements in your opto-mechanical systems

Essential Macleod v8.15.174

The Essential Macleod program contains all the essentials for the design and performance calculation of optical coatings. In particular it will calculate a wide range of performance parameters of a given coating design including the usual reflectance and transmittance magnitude and phase, but also color, ultrafast, ellipsometric quantities and from the zero’th up to the third derivative as a function of wavelength. It will estimate the effects of random errors in the layers. It will refine existing designs to improve their performance and it will synthesize designs that start with virtually no instructions other than the materials to be used and the performance that is targeted. It includes allowance for layer packing density. It has powerful design editors to make it very easy to create or change even the most complex designs. It also maintains the files that contain the optical constants of materials. The Essential Macleod will also calculate performance of series of different substrates, with or without associated coatings and it will perform a wide range of analytical functions such as generating admittance diagrams and electric field distributions. It has a completely flexible system of variable units.

The Essential Macleod is equipped to export coating designs to the ZEMAX and Code V optical design packages, It will also export performance to the LinkSIM simulation tool.

Optional enhancements add a virtually limitless range of possible performance functions, run sheets and monitoring curves with links to thin film monitors.

The package is an integrated whole with the operation controlled almost entirely from menus. The menu commands are designed to permit the user to indicate what has to be done without needing to indicate how. To calculate an aspect of performance, for example, the user simply tells the package to produce a plot or a table. The underlying operation and organization is completely automatic. The description that follows, therefore, concentrates on the menu commands, what they are and what they do. It is purely a description of the operation of the software package. It does not go into details of the calculation techniques nor does it discuss design technique

The Essential Macleod uses a Multiple Document Interface (MDI). A document can be a plot, a table, a design, a list of materials and so on. Multiple Document Interface means that many documents may be displayed at once, the total number being limited by the capabilities of the computer and of the Windows installation. One document at a time is active. The menu bar changes as the active document changes so that the menu commands always apply to whichever of the open documents is the active one. For example, if a plot is active then the Edit menu will apply to the plot and will permit such things as changing the parameters of the axes. The user will find that it is often useful to be able to keep several designs open simultaneously. Should the capacity of Windows or of the computer be exceeded then the user will simply be requested to reduce the number of open documents. There is no need constantly to keep track of what is open. We do recommend, however, that unnecessary documents should be closed to avoid clutter.

Throughout the operation of the package, designs and specifications are saved to various files. The principal files are known as design files and they contain not just the sequence of layers but also the calculation parameters that should be used to evaluate the design. If a design is passed to refinement, the refinement specification also becomes part of the design file. The operation of saving the design and parameters can be manually performed at any time by choosing the appropriate menu item but it is also automatically initiated at those stages where there is a danger that something might otherwise be lost. In spite of this automatic feature, we do recommend that the user acquire the habit of saving the work at intervals. In particular when moving from one design to another it often seems convenient just to write the new design over the old. However, if the existing design is important the editing process will change it perhaps beyond recovery. No automatic save is initiated whenever a design is edited - editing is a very simple and straightforward process. Before beginning major editing, where a design is going to be substantially altered, it is good practice to save the design twice, once in the existing design file, thereby preserving the current design for later recall, and once in a new design file, which can then be edited without fear of changing the original. You may find this approach useful in other applications such as word processors also.

In the Essential Macleod the optical constant information for the thin film materials is kept in separate files in one or more materials databases. In the designs, the materials of the films and substrate are referred to explicitly by name (normally the chemical formula). A material database consists of a set of materials files together with control files that are kept in a separate folder, the path being the identifier for the database. Many different material databases may exist together. This is a particularly useful feature of the Essential Macleod and we encourage the user to make full use of it. Separate databases could be used, for example, for infrared materials as distinct from visible materials with wavelength stated in microns rather than nanometres. Alternatively, different databases could be used for different customers or for different plants or processes. In order to keep track of the particular database that was used to generate a design, information on both the database and the number/name conversion for the materials used, is stored in each design file. This information is compared with the existing database when a design file is read and only if an exact match is found can the calculations proceed without intervention. The material database can easily be changed but only when there are no open documents. The General command in the Options menu opens the form that contains the necessary command for changing the material database. A number of facilities are provided to simplify the maintenance of many different material databases. These are described later in the manual.

ESI.PROCAST.V2007

We are proud to announce, only six months after the previous release, a new release of ProCAST 2007, the leading finite element software package for foundry simulation.

This new version brings additional new features in meshing, processing capabilities, viewing and numerous improvements in product performance.
The ProCAST solutions include automatic mesh generation, thermal analysis with radiation effects, flow analysis for mould filing, fully coupled thermal, flow and stress analysis and advanced metallurgical options.

The following main improvements deserve to be highlighted (for more information, please contact your ESI Group’s representative).

SOLVERS

True 64 bits executables for ProCAST solvers are now available on Windows for both scalar and DMP versions (64 bits executables are available on Linux, as before).

ASSEMBLY


The assembly algorithm was improved in order to be more automatic and powerful.

FADING

Nodular cast iron (SGI) is obtained by a Mg treatment of the melt. The graphite formation tends to diminish as the interval between the treatment and the solidification increases (fading effect). As a consequence, the expansion effect will be reduced as graphite formation is decreasing. This will of course have an effect on the amount of porosity. ProCAST 2007 integrates the modeling of graphite fading in SGI and therefore allows better porosity modeling.

One illustration of this new model is presented above for two extreme cases: on the left the FADING value is one while on the right the FADING value is zero. It is seen that in this latter case the porosity is decreased to zero.

PARALLEL PROCESSING

Continuous efforts are being devoted to improve the scalability, repeatability and availability on various platforms of the ProCAST DMP solver. The following improvements have been made in ProCAST 2007:

The Microstructure module is now available in the DMP solver,
The Freckle calculation is now available in the DMP solver,
The Core blowing option is now available in the DMP,
Improved performance of the stress parallel solver,
Improvements in lost foam modeling and interpenetrating mesh option.

CORE BLOWING

ProCAST allows now improved modeling of the core blowing process. When modeling the sand injection process, the air and sand are modeled as a homogeneous fluid in which the air-sand mixture is treated as a single phase. Thus, the process is considered as a filling with ad-hoc material properties and boundary conditions.

FLUID FRONT TRACKING

The "Fluid Front Tracking indicator" is based on an algorithm which is calculating in the solver the tracking of the free surface front. This allows identifying the locations where oxides and impurities trapped at the free surface are most likely to end-up as

ADINA-v8.4.2 (c)Adina

The ADINA System consists of the following modules:

ADINA-AUI The ADINA User Interface program (AUI) provides complete pre- and post-processing capabilities for all the ADINA solution programs.
ADINA-M The ADINA Modeler (ADINA-M) is an add-on module to ADINA-AUI that provides solid modeling capabilities and direct integration with all other Parasolid-based CAD systems.
ADINA The premium finite element program for linear and highly nonlinear analyses of solids and structures.
ADINA-F CFD program for the analysis of compressible and incompressible flow with state-of-the-art capabilities for moving boundaries and automatic remeshing.
ADINA-T Module for the heat transfer analysis of solids and field problems.
ADINA-FSI The ADINA-FSI (fluid structure interaction) program is the leading code used by industries for fully coupled analysis of fluid flow with structural interaction problems. This module is available to users who license both the ADINA and ADINA-F modules.
ADINA-TMC This module provides capabilities for thermo-mechanical coupled (TMC) analysis, including analysis of contact with heat transfer. By licensing both the ADINA and ADINA-T modules, the user automatically has access to this module.
CAD Interfaces Through ADINA-M, users can directly import Parasolid-based (e.g., Unigraphics, SolidWorks, and SolidEdge) CAD geometry. We also provide interface programs to major systems such as
I-DEAS and MSC.Patran. Where a direct interface is currently not available (e.g., CATIA), the geometry can

DYNAFORM V5.6 (c)ETA

DYNAFORM Version 5.6 release note:
The release of DYNAFORM Version 5.6 contains many enhancements that certainly improve your stamping design and development capabilities. Some of the major improvements include:
Enhanced Pre Processor Functions:
1. New layout for line functions from CREATE, DELETE, EDIT/MODIFY, TRANSFORM to DISLAY. Integrate TRANTSLATE, ROTATE, MIRROR and SCALE in one dialog. Translate line can be completed from LCS to LCS.
2. New layout for surface functions from CREATE, DELETE, EDIT/MODIFY, TRANSFORM to DISPLAY. Integrate TRANTSLATE, ROTATE, MIRROR and SCALE in one dialog. Translate surface can be completed from LCS to LCS.
3. Add Mesh to Surface function. User can create surfaces from mesh.
4. Add brand new Extend Surface function. User can expand untrimmed surfaces.
5. Add brand new Check Surface function.
6. New layout for Element functions from CREATE, DELETE, EDIT/MODIFY, TRANSFORM to DISPLAY. Integrate TRANTSLATE, ROTATE, MIRROR and SCALE in one dialog. Translate element can be completed using LCS to LCS.
7. Drag Mesh function is updated. Thick Shell or Solid Elements are created using this function.
8. Add Trim Element function in Element dialog box. The user can select one or several trim lines to trim elements.
9. Add Lance Element function in Element dialog box.
10. New layout for Node functions from CREATE, DELETE, EDIT/MODIFY, TRANSFORM to DISPLAY. Integrate TRANTSLATE, ROTATE, MIRROR and SCALE in one dialog. Translate node can be completed using LCS to LCS.
11. Add brand new Check function to check the deviation between surface and mesh.
Improved Blank Size Engineering Module:
1. Develop special GUI for the Trimline development.
2. Support Multi-step Unfold function.
3. Enhanced Middle and Group surface functions.
4. Improved Blank Development function.
Redesign Die Face Engineering Module:
1. Improved DFE Preparation GUI.
2. Add Double Attach function.
3. Allow input for pre-designed binders.
4. Improve Surface Edit function. User can easily edit surfaces.
5. Add Side-Step function to allow user to easily fill end of geometry.
6. Inner Fill function is improved with Control Line.
7. Element Morphing function is improved. Over crown can be easily created.
8. Binder function has been improved to support 2-D binder shape edition. User can
select Reference Line feature line to edit the control line in the 2-D edition dialog.
9. Add brand new Flange On Binder function.
10. Add brand new Butterfly Binder function.
11. Addendum function is improved.
12. Binder trim function is improved.
Enhanced Setup Module:
1. Support Geometry offset and Contact offset.
2. Support Multi-stage stamping in one setup for line die simulation.
3. Add QuickSetup GUI for Tube Rotary Bending.
4. Support Super Plastic Forming simulation.
5. Support Solid/Tshell blank element.
6. Support Thermal Forming Simulation. Add thermal solver parameters and thermal material models.
7. Material Library is improved. User can easily define his/her material library.
8. Improve Blank Trim function. User can trim inner boundary and outer boundary.
Springback Compensation (SCP) Module:
1. Add brand new Springback Compensation module.
2. Add SCP solver.
New Post Processor Features:
1. Improved the index file. Index File Transfers Part Name, Blank Material, FLD, Bead Information and multi-stage information to the Post-processor.
2. User Defined Contour function is added. User can Create, Modify and Delete User Defined Component.
3. FLD plots can be scaled.
4. Interface Pressure can be checked.
5. Face Reflection Function is improved. Face Reflection simulation using several light strips to check smooth surface. Distorted light strips indicate surface’s curvature is uneven.
6. Brand new Tool Wear function. All necessary data needed for wear depth calculation are supplied from the LS-DYNA interface force database file (d3plotint). The tool wear interface is displayed after opening d3plotint file.
7. Add brand new Painted blank function. User can paint the select pictures on the deformed blank.
8. Support plot and animate thickness and thinning for Solid and Tshell Element.
9. Support process multi-stage simulation result.

IMAGINE.AMESim.v4.3

A graphical environment for modeling, simulation and analysis of dynamic engineering systems, AMESim is based on a large set of validated libraries issued from different physical domains. AMESim allows you to access rapidly the ultimate goal of modeling: the analysis and optimization of your design.

Focusing on physics, AMESim frees the engineer from numerical aspects. The basic element concept, which lies behind each model, provides basic engineering elements that can be combined to describe all functions of the component or system in the model. Thereby, engineers don't have to worry about code writing.

User Interface
The AMESim graphical interface enables the user to build complex models by choosing among a collection of components. The resulting sketch is then easily understandable, as close as possible to what a design engineer could expect. Various levels of models can be selected for each component.

The user can also set parameters and units in a friendly way. The modeling process divided into four modes (build sketch, select model complexity, set parameter and finally, run simulations and perform analysis) enables the user to work quickly and efficiently.

Multi-domain system design
The AMESim platform provides a simulation environment for multi-domain system design with a large set of libraries covering multiple domains and applications. Focusing on physics, AMESim offers both a structured multiport approach for the modeling of physical systems and a block diagram approach for control systems. This effective and clear concept for communication of model information provides a clear-cut technique to model physical systems, capture and re-use engineering knowledge, and finally to greatly facilitate the sharing of engineering efforts.


Key Points
Adaptability & Reusability
Multi-domain simulation platform
Structured libraries of physical models
Various model complexity levels
Designed to capitalize and share know-how
Comprehensive documentation
Open Platform
Interface with CAE software such as Matlab®, Simulink®, Flux® or in-house code
C Code generation
Access to library's source code
Cross platform: Windows, UNIX and Linux
Unrivaled Numerical Core
Automatic and adaptive selection of the integration method
Discontinuity handling
Model linearization
Advanced Features
Sensitivity analysis
Parametric study analysis
FFT and Linear analysis
HTML report generator
Animation

Comsol-Multiphysics-V3.4

COMSOL Multiphysics 3.4 provides fully parallelized meshing for assemblies straight out of the box. A new boundary layer meshing feature in version 3.4 enables users to mesh thermal boundary layers, charged double-layers in AC/DC applications, or viscous boundary layers in fluid-flow applications more efficiently, with greater accuracy, and with less memory consumption than previously possible.

A major upgrade to COMSOL Multiphysics’s iterative methods pushes solver performance for fluid dynamics to new heights. For example, new, state-of-the-art Galerkin Least Squares (GLS) stabilization techniques now complement COMSOL’s iterative solvers, enabling engineers and scientists to compute large fluid flow problems with millions of degrees of freedom. A segregated solver with an easy-to-use interface, new in version 3.4, reduces memory consumption significantly when computing large problems, such as fluid-structure interaction (FSI) or wave propagation in thermally deformed structures. When compared to its predecessors, COMSOL Multiphysics 3.4 solves fluid-flow problems up to five times faster.

COMSOL Multiphysics 3.4 also offers users a new suite of postprocessing tools for computing geometric properties such as volume, area, center of gravity, and moment of inertia. Even simulation results can be presented in exciting new ways with version 3.4’s expanded palette of color scales.

Multiphase flow and free convection in the Chemical Engineering and Heat Transfer Modules
Users of the COMSOL Chemical Engineering and Heat Transfer Modules can now step up their simulations to include variable-density flow and free convection. Engineers will find these new capabilities particularly useful when solving coupled flow and conjugate heat transfer problems commonly encountered in electronic cooling and heat exchanger analyses. For applications such as microfluidics, multi-species convection, and reacting flows, COMSOL Multiphysics 3.4 has been enhanced with additional multiphysics modeling interfaces for turbulent and laminar flow with variable densities due to variations in composition.

The Chemical Engineering Module has been improved with a powerful modeling interface for the simulation of multiphase flow. With it, users can now simulate bubbly flows such as in scrubbers, aerators, bioreactors, and food-processing equipment effortlessly. Users can also easily set up mixture models for simulating emulsification, sedimentation, and other separation processes common in the chemical, pharmaceutical, and food-processing industries.

The Heat Transfer Module has been greatly enhanced by the introduction of boundary layer meshing and by improvements to COMSOL’s solver technology. Boundary layer meshing provides engineers and scientists with greater accuracy yet requires fewer elements for simulating electronic cooling, heat exchangers, and heat losses to solid structures in mechanical design. Also new in the Heat Transfer Module is the ability to model 3D surface-to-surface radiation using the memory-saving 2D axisymmetric modeling domain.

Parameter estimation in COMSOL Reaction Engineering Lab
Upgrades to the COMSOL Reaction Engineering Lab® include a powerful new interface for running nonlinear parameter estimations on multiple sets of experimental data. In addition, it is now possible to select which parameters to estimate and which parameters to keep constant in each estimation run. Outputs now display with confidence intervals and standard deviations.



SPICE import in the AC/DC Module and new lumped ports in the RF Module
Version 3.4 makes it easy to build and run COMSOL models as part of SPICE-based circuit simulations thanks to the AC/DC Module’s new SPICE user interface. Another exciting new feature for electronics, electrical components, geophysics, and electrochemistry applications is small-signal analysis for AC impedance studies. Users can also easily model electric motors and generators through a new interface supporting periodic boundary conditions and sector symmetry. Additionally, a new periodic boundary condition user interface has been introduced in the RF Module along with an improved interface for lumped port boundary conditions, which is ideal for wave propagation in transmission lines and circuit boards.

Fatigue analysis enhances the Structural Mechanics Module
The COMSOL Multiphysics Structural Mechanics Module now lets users predict high- and low-cycle fatigue damage. A suite of COMSOL Script functions calculate fatigue damage from inputs made up of loading data and deterministic, stochastic, or even nonproportional material fatigue data.

COMSOL Multiphysics 3.4 Highlights
Parallelized meshing, assembly, and solving on multicore and multiprocessor computers
Memory-efficient fluid flow solvers for chemical engineering, heat transfer, and microfluidics
Segregated solver minimizes memory consumption for large multiphysics problems
Improved postprocessing including geometric properties such as center of gravity
Easy modeling of electronics cooling and free convection with interfaces for variable-density flow
Boundary layer meshing for representing boundary layers in fluid flow, heat transfer, and electromagnetics
Bubbly flow interfaces for modeling of scrubbers, aerators, bioreactors, food processing equipment, and boiling
Mixture-model two-phase flow interfaces for simulation of emulsification, sedimentation and separation processes as well as fluidized beds
Nonlinear parameter estimation
Piezoacoustic multiphysics modeling of microphones, ultrasonic transducers and MEMS devices
Full-wave 3D RF analysis of printed circuit boards and transmission lines with lumped port boundary conditions
Fatigue analysis

Nupas 2007 v5.2(c)Cadmatic 3d hull

Nupas-Cadmatic ship design software was developed through a joint venture between Cadmatic Oy and the Dutch software design company, Numeriek Centrum Groningen B.V.
A Nupas-Cadmatic 3D-model of ship a ship engine room with machinery layout, piping and HVAC

By combining our resources we have created a design software package that provides better design solutions than traditional market offerings.Nupas-Cadmatic is a unique CAD/CAE/CAM design software package for shipyards and design offices interested in improving their efficiency, design and production. The open software lends itself to efficient hull-, machinery-, piping-, outfitting-, and interior design while efficiently creating the required production and maintenance information. The software supports concurrent and distributed design leading to more cost efficient and effective design.

3D Hull Engineering, the main hull modelling module, is the core of the Nupas-Cadmatic Hull system. It is used for modelling of the hull structure from the early design up to the detailed and production engineering of hull blocks, panels and parts.
The 3D Hull Engineering module distinguishes itself from other CAD/CAE/CAM systems in that it is extremely easy to use. The intuitive user interface guides the hull designer with maximum assistance while creating structural components like decks, bulkheads, stiffeners, shell frames, girders, flanges, brackets etc.
Hull structures are stored topologically, meaning that relations between structural components and relations with the hull shape allow fast and easy re-use of information without redoing work. The effects of modifications on a topological structure are automatically carried through to the related structural components.
The 3D Hull Engineering module includes powerful copy functions, parametric definition of yard standards and many automatic mechanisms like part and panel numbering, marking lines, standard bracket selection, part coding etc. taking away many of the hull designer's daily worries and routine tasks.

The project library used by the 3D Hull Engineering module consists of a collection of all necessary yard standards for cut outs, profile end shapes, stiffener types, brackets, holes and other structural entities. Besides the yard related standards, software settings and project specific parameters are also stored and maintained in the project library.

Zuken.CR5000.Board.Designer.v10

Zuken's CR-5000 Board Designer provides an intuitive, integrated environment for designing PCBs, BGAs and MCMs. It serves to guide the user, via a common user interface, from schematic capture, floorplanning, placement and routing, analysis and into manufacturing. It operates seamlessly across Unix and Windows platforms combining the functionality of a high-end tool with ease of use. While rules are constant throughout the design process, they are dynamically linked to ensure flexibility and consistency.

Benefits
1. A single, intuitive environment with a coherent approach throughout the design process, easy links between tools, and a common database and libraries.
2. Rules-driven design for correct-by-construction outcomes.
3. An optimized combination of automatic, semi-automatic and interactive functionality to maximize design productivity.
4. Design partitioning that facilitates intelligent, concurrent engineering: especially useful for large or complex products and for the re-use of proven circuits.
5. Re-use of proven circuit blocks saves time.

The CR-5000 EDA design suite provides the most advanced PCB design functionality currently available. It is constraints driven, from schematic capture through board layout, to the output of manufacturing data. This means that the rules you apply early in the design process are maintained right through to manufacturing. So products are right first time, manufacturable first time, and get to market fast. A common component database is used throughout the process, so design, bill-of-materials (BOM) generation and manufacturing processes are based on a common data set. Efficiency is driven up, waste and re-work are eliminated. Amongst its other advanced features, CR-5000 supports advanced technologies such as build-up to facilitate miniaturization, automatic routing to speed up and optimize PCB layout, early design verification to eliminate design iterations (particularly in high-speed circuits), and RF design. It enables design re-use to prevent unnecessary duplication of effort, design partitioning to facilitate teams of individuals working on the various elements of a design simultaneously, and 3D viewing/editing for component placement and package optimization. CR-5000 is constantly developed and adjusted to new technologies in co-operation with our customers, to enable them to face to the challenges of the future.