IAR-Embedded-Workbench-for-AVR 5.11

IAR Systems creates development tools for embedded systems since 1983. The governing principle has always remained the same: to provide premium tools that are well integrated, generate efficient code, and last but not least are pleasant to work with.

IAR Systems cooperates with the most renowned companies in the industry—semiconductor vendors and manufacturers of emulators, RTOSes and other products—to provide embedded developers with a choice of flexible and powerful development tools.

RTOS, TCP/IP and USB stacks
IAR PowerPac is an integrated middleware family that combines a small memory footprint RTOS and a versatile file system. It is suitable for all types of embedded applications in different industries; for example, test and metering equipment, industrial equipment, telecom,munication medical devices and consumer electronics.

IAR PowerPac is available at an innovative and low-risk per-seat license model, without royalty fees. IAR PowerPac is an add-on product to IAR Embedded Workbench and is currently available for ARM processors and ColdFire.

IAR Systems is also a world-wide distributor of products from Micrium, available for a wide selection of microcontroller architectures.
Development kits
Each development kit contains all the hardware and software you need to get going quickly:


IAR KickStart Kit is a complete evaluation environment for embedded system applications available for a vast selection of targets
IAR Advanced Development Kit is a complete development environment for embedded system applications based on ARM processors

CoWare Signal Processing Designer (SPD) V2007

CoWare Signal Processing Designer
Implementing Algorithms for Platform-Driven ESL Design
Highlights

Industry's fastest, production proven signal processing simulator
Fully supported on Windows and Linux
4000+ models with source code
Unique standards reference libraries
Fully integrated with MATLAB® and Catalytic MCS tools
Fully integrated into CoWare platform-driven ESL design solution
RTL cosimulation support for Cadence Incisive® and Mentor Modelsim®
RTL code generation for Synopsys DesignCompiler® and Cadence Encounter®
Analog-Mixed Signal (AMS) cosimulation with Cadence Incisive®
One-click analysis
Powerful polymodeling capability
State-of-the-art GUI for maximum productivity
Scalable XML database
Automated model migration from SPW designs
Overview
CoWare® Signal Processing Designer (SPD) accelerates the design of complex, digital signal processing (DSP) systems. It is a C-based modeling and simulation environment that facilitates structured modeling and model reuse across design teams. Its efficient creation of complex DSP system models and extremely fast simulation makes Signal Processing Designer the premier choice for today's complex, multi-standard designs in the wireless and multimedia markets. It is tightly integrated with the CoWare Platform Architect and CoWare Processor Designer products.

Petrel 2008.1

The 2008.1 release of Petrel* software brings to the
petrotechnical desktop not only improvements over
the traditional geophysics, geology, and engineering
tools but cutting-edge technology.
NEW ENHANCEMENTS
Innovation
■ Graphics processing unit
(GPU)-based multivolume
rendering and geobody
extraction
Workflow
■ Autotracking improvements
■ Synthetic trace import
■ New fault surface
triangulation algorithm
■ Inclusion of levees in channel
modeling
■ Equipment and hydraulic
fractures for completions
■ Gradual local gridding option
■ Sector modeling
Usability
■ Item selection from 3D/2D
windows
■ Annotation of horizons/faults
in interpretation window
■ Seismic data prefetched to
cache for improved performance
■ Well symbol control for
subfolders
■ Improved kriging performance
on large datasets
■ Volume calculation

The 2008.1 release of Petrel* software brings to the
petrotechnical desktop not only improvements over
the traditional geophysics, geology, and engineering
tools but cutting-edge technology.

Volume and geobody interpretation
3D seismic interpretation has traditionally been per-
formed by picking points on 2D displays of 3D seismic
cubes. The new Petrel Geobody interpretation
module employs state-of-the-art volume-blending
technology to quickly isolate, extract, and integrate
a body directly into a property model for true 3D
volume interpretation. This allows users to interac-
tively blend multiple seismic volumes, isolate areas
of interest, and then instantly extract those areas into
a 3D object called a geobody. This “what you see is
what you pick” approach to volume interpretation is

meters, allowing a clear picture of the depositional
environment. These geobodies can be created or
directly included in the 3D geological model, provid-
ing a complete seismic-to-modeling workflow.

Horizon interpretation
Interpretation is further improved by enhancements
to autotracking workflows, including independent
refinement of the dip angle of the tracked event in
both inlines and crosslines for improved accuracy
in 3D volume inter
possible with both an asymmetrical and a symmetrical wavelet.
Asymmetrical wavelet tracking allows the user to focus on the data
either above or below the event to guide tracking, greatly enhancing
results particularly in areas of low data quality.

GEOLOGY AND MODELING
Performance
The oil industry today is constantly exploring ways to build bigger and
more detailed reservoir models. However, larger models require longer
process run times and the need to work faster becomes critical. Petrel
2008.1 software improves performance by supporting multithreading for
depth conversion, establishing horizons, volume calculation, some geo-
metrical modeling methods, and property modeling (kriging)—freeing the
user’s time for other work or for running multiple realizations. In addition,
enhanced data-tree performance for projects with large numbers of tree
nodes has improved speed and performance when scrolling in the data
tree, copying and reparenting well logs, and applying saved searches
with large numbers of well tops displayed.

RESERVOIR ENGINEERING
Sector model
The ability to test models in a small portion of the field is essential
because the simulation of big models is so time-consuming. The new
Petrel 2008.1 release enables the creation of single-sector models,
allowing the user to perform quick simulations on small areas of the
full field model, which requires less memory and eliminates the need
to rewrite or reexport the dataset.

Hydraulic fractures
Hydraulic fractures are commonly used to improve the inflow perform-
ance of wells in low-permeability reservoirs. These fractures are usually
defined in simulation using nonstructural grids around the fracture plane,
increasing the computation time because of the complexity of the mesh.
However, fractures can also be defined by length, height, permeability,
and orientation in the simulation model and can be simulated by modify-
ing the well productivity index (PI) and transmissibility of surrounding
cells, achieving the same result as with complex grids. Petrel 2008.1
software allows users to model fractures in full field simulation models
in this way, which has a negligible impact on run time but captures the
effects of flow patterns at the global model scale.

Compositional fluids
Volatile oil and gas condensate reservoirs cannot be modeled accurately
with conventional black-oil models. The ability to model fluids at varying
levels of approximation is essential, because real hydrocarbon fluids
can be extremely complex mixtures. The Petrel 2008.1 release provides
the ability to import and use equations of state in simulation, define
sample compositions, and plot phase envelopes for a better under-
standing of the fluids in the reservoir.

Ansoft.Maxwell. v12.0

Maxwell is the leading electromagnetic field simulation software used for the design and analysis of 3D/2D structures, such as motors, actuators, transformers and other electric and electromechanical devices common to automotive, military/aerospace, and industrial systems. Based on the Finite Element Method (FEM), Maxwell accurately solves static, frequency-domain and time-varying electromagnetic and electric fields.

Maxwell v12 improves engineering productivity, reduces development time, and assures first-pass design success. New Distributed Analysis and multi-processing enhancements allow users to solve very complex, electromagnetically large geometry faster and to expand beyond what they ever thought possible with simulation technology. Additionally, Maxwell v12 includes new automation features, user-interface refinement, and data linking capability, making it easy to design, simulate, and validate complex, high-performance electromechanical and electromagnetic devices.

What s new in v12?

3D electric transient solver
Revised interface for Maxwell 2D:
Improved 2D modeling with editable geometry history
Extended undo/redo history
Complete scripting capability
Enhanced post-processing
RZ support for AC conduction
Animated field plots of parametric solutions
Multiple designs in a single project
Multiple projects in a single desktop
Advanced product coupling capability with Simplorer? HFSS?and ePhysics?
New report editor for better usability
New Genetic Algorithm in Optimetrics?
Microsoft Windows?Server 2003 x64 Edition suppo

Agilent.GENESYS.2008.01.SP1

Agilent Technologies Inc. (NYSE:A) announced that it has shipped GENESYS 2008, the next major release of its GENESYS electronic design automation (EDA) software. GENESYS 2008 features LiveReport, a new design capability that streamlines the user interface and automates the documentation process for easy communication and reuse for RF and microwave component and subsystem designers.


LiveReport helps designers overcome the complexities of working with large, multi-design projects. It captures living views of schematics, layouts, graphs and equations onto a single interactive document. Clicking on any image on a LiveReport page allows the designer to modify schematics, change markers and plots, and zoom layouts from a dashboard-like interface. When the design is complete, the LiveReport page can be printed at high resolution or cut and pasted into Microsoft Windows(tm) applications. A print preview function offers complete control over the appearance of the report — the answer to a much-requested enhancement to the GENESYS package.

"The GENESYS 2008 interface is a product of customer requests," said Daren McClearnon, product manager with Agilent's EEsof EDA division. "The result is a simpler working model that helps you get work done faster. While there is plenty of technical contribution to GENESYS 2007, longtime GENESYS users will see this as a milestone release. The long-term architectural investments are finally paying off, making GENESYS a streamlined, exciting platform."

GENESYS 2008 contains a number of simulator enhancements, including:

17 new nonlinear device models that enable RF power amplifier design, microwave downconverters, high-speed analog and wireline applications
Improved phase noise in the harmonic balance simulator and an enhancement to Spectrasys to predict the RF system noise effects of phase-locking many local oscillators to a common, coherent frequency reference; these enable high-performance receiver architectures with breakthrough sensitivity and throughput
New sources, measurements and defined "paths" in Spectrasys, which characterize large-signal distortion in complex architectures under sophisticated, multi-format signal conditions with interferers
Dozens of new toolbar buttons and right-click operations simplify complex tasks down to single button-clicks, saving time and making GENESYS 2007 faster than ever. Implemented suggestions from users include common tasks such as on-screen parameter editing, saving parts to a custom library, deactivating components, and turning off window visibility to maximize the working schematic area.

New features in GENESYS 2008 are available as free upgrades to supported customers. Supported GENESYS users are encouraged to visit the Agilent EEsof Knowledge Center to download their new release.

About GENESYS
Developed originally by Eagleware-Elanix and acquired by Agilent Technologies, GENESYS is an integrated EDA software package for RF and microwave design. Its configurations focus on RF circuit and system design at an unmatched price. From initial system architecture through final documentation, GENESYS provides state-of-the-art performance in a single, easy-to-use design environment that is fast, powerful and accurate.

Altair.Hyperworks.V9.0 For win32 &Win64&Linux

Newest version of Altair's simulation platform delivers on-demand access to ISV applications and offers multi-core licensing business model

TROY, Mich., May 20 /Xinhua-PRNewswire/ -- Altair Engineering, a global provider of technology and services empowering client innovation and decision making, today announced the release of Altair HyperWorks 9.0, the next generation of its popular integrated suite of computer-aided engineering (CAE) software applications.

HyperWorks is an enterprise simulation platform to support product lifecycle management (PLM) processes. It is the leading simulation-driven design solution for product development across the world's top corporations.

"Over the past decade, Altair HyperWorks has become the preferred simulation platform for the worldwide advanced manufacturing community," says James R. Scapa, president and CEO of Altair. "Through advancements in simulation technology, a value-driven business model and superior customer support, the adoption of HyperWorks continues to outpace the CAE market with a five-year compound annual growth rate (CAGR) of more than 25%."

Grid Enablement and New ISV Partner Program

The release of HyperWorks 9.0 is the first engineering simulation solution to deeply embed grid computing management tools with compute-intensive CAE software applications. HyperWorks 9.0 clients can now use unallocated HyperWorks units in their existing pool to immediately access Altair's popular PBS GridWorks on-demand grid-computing technology suite at no incremental cost. This common licensing model allows corporations to virtualize their global computing infrastructure -- maximizing the throughput of analysis jobs as well as the utilization of hardware and software resources.

In addition, HyperWorks 9.0 extends its patented business model to deliver on-demand, third-party software applications. Participating partners and the formal roll-out of Altair's partner solutions program will be announced on Wednesday May 21st, 2008.

Next-generation Solver Technology and New Multi-core Licensing Business Model

With the release of HyperWorks 9.0, Altair has integrated all of its linear and nonlinear finite-element solvers into a single solver application. RADIOSS 9.0 now delivers a robust solution for simulating linear statics and dynamics, nonlinear transient dynamics and fluid-structure interaction events. This consolidation and integration uniquely positions RADIOSS in the CAE solution market and further increases the value of HyperWorks. From a user perspective, RADIOSS 9.0 simplifies multi-disciplinary analysis studies and data exchange between analysis types. Business benefits include lower software licensing costs and simplified IT administration.

"The advent of cluster and multi-core computing environments requires new, more affordable software licensing models," says Jeffrey M. Brennan, vice president of Altair's HyperWorks division. "Our unit-based licensing model -- already a market differentiator -- has been further enhanced to allow companies to take full advantage of multi-core computing environments with our solvers through virtualization and an aggressive pricing model."

Extended Interoperability and Microsoft Office Integration

The open-systems design of the HyperWorks platform allows engineers to seamlessly work with any CAD solution, any solver, and any pre- and post-processing environment. The 9.0 release extends this interoperability even further to include Microsoft Office suite applications fostering enterprise collaboration and information sharing. This direct integration not only offers efficiencies to the reporting process but also will support design robustness investigations through a direct integration with Microsoft Excel and HyperStudy, Altair's design optimization study application. HyperGraph and HyperView post-processing applications now export directly to Office applications, as well.

New Capabilities and Functionality

"This release is significant on many different levels," says Dr. Uwe Schramm, Altair vice president of product technology. "Substantial investments were made to evolve the graphical user interface to quickly gain new user acceptance and shorten learning curves for enterprise deployments. Industry specific advancements, especially for our rapidly growing aerospace community, have been made across all of our core products including HyperMesh, HyperView and OptiStruct."

Modeling and visualization advancements include:

-- Enhanced "Windows-like" graphical user interfaces (GUI)
-- HyperCrash: A new automotive crash pre-processor
-- New rapid HEX solid meshing capabilities
-- Shrink-wrap meshing to accelerate the creation of large solid models


Optimization and data management advancements include:

-- Rapid multi-body dynamics optimization
-- Free-shape optimization with manufacturing constraints
-- Free-sizing optimization for composites
-- Model assembly, batch meshing and performance data management
automation

For more information on the HyperWorks 9.0 release, training schedules, regional roll-out events and to request a HyperWorks 9.0 demonstration, please visit www.altairhyperworks.com/hw9 .

Agilent.RFDE.V2008 FOR Linux (RF Design Environment )2008

RF Design Environment (RFDE) 2008 includes a number of important enhancements. Among them are the following:
RF/mixed-signal IC design in the Cadence environment.

RFDE makes available important frequency-domain and mixed-domain simulation technologies; optimization and statistical design tools; additional device, system, and behavioral models; and powerful data display and post-processing.

Improved DC, AC and Transient simulation speed
Improved Momentum simulation speed on multi-core platforms
Remote simulation with single bundled license
New substrate editor tool
RFDE 2008 is supported on both 32 and 64-bit versions of the following operating systems:

Linux RHE4
SUSE SLES 9
Solaris 10

AGILENT.IC-CAP.V2008

IC-CAP (Integrated Circuit Characterization and Analysis Program) is a device modeling program that provides powerful characterization and analysis capabilities for all of today's semiconductor modeling processes.

IC-CAP offers device engineers and circuit designers state-of-the-art modeling software that performs numerous modeling needs including instrument control, data acquisition, graphical analysis, simulation, optimization, and statistical analysis.

All of these processes are combined into a flexible and intuitive software environment for efficient and accurate extraction of active device and circuit model parameters. IC-CAP also provides the power to build model libraries for Agilent EEsof EDA and other simulators.

The Target Modeling Extraction Package
The new extraction package, for use with Agilent's Integrated Circuit Characterization and Analysis Program (IC-CAP) software allows engineers to extract CMOS models based on process target data and when available, traditional I-V curves.

Traditional CMOS modeling uses extensive I-V and C-V data for various device geometries. These are typically obtained from time consuming measurements when the process is stable and mature. To extract accurate CMOS models much earlier in the design cycle, Target Modeling uses process control monitor (PCM) data, typically fast single bias point measurements, which are commonly available in the early stages of process development.

The Target Modeling Package includes the following features:

A dedicated User Interface specifically designed for this application
Import of PCM data and related bias information form Excel spreadsheets
Import and display statistical information of PCM data (mean and spread values)
Direct support of BSIM3, BSIM4, PSP and BSIMSOI models
Support for major commercial simulators including Agilent's Advanced Design System (ADS), Cadence's Spectre and Synopsys' HSPICE.
Display, tune and optimize user defined scaling and I-V diagrams
Customizable automatic generation of HTML reports
Open architecture allows import and use of traditional I-V traces in conjunction with PCM data plots.
Package Overview
The Extraction Package includes a dedicated UI main window that manages the PCM data import and the creation of scaling and I-V diagrams. Device information and PCM data are imported directly from excel spreadsheet. Convenient wizards enable you to define subsets of devices and derive PCM data scaling diagrams (e.g. Ion vs. L, Ioff vs. W, etc.).
Figure 1: Target Modeling Tool Main Window and example of PCM scaling diagram (Ion vs. L).

A dedicated user interface enables you to combine diagrams into multiple plots (IC-CAP's Multiplots). The powerful IC-CAP Plot Optimizer tool enables you to conveniently select model parameters and tune and optimize scaling and I-V plots.

Figure 2: Diagram Configuration Page and an example of MULTIPLOT diagram including several scaling diagrams and one I-V curve.

Powerful simulator links to ADS enables real time tuning performance when simulating multiple devices. The extraction package benefits of an improved IC-CAP link to HSPICE made available with IC-CAP 2006B Add-on 3 and HSPICE 2007.03-SP1.

Availability
The IC-CAP Target Modeling Package (85199KL) is available now as part of the current IC-CAP 2008 release. IC-CAP parameter extraction software is available now; contact your local Agilent EEsof EDA sales engineer for pricing.

Worknc-G3 -v19.13 crack

WorkNC G3 stands for 'third generation' and signifies the arrival of the software's third completely new user interface along with expanded and enhanced functionality.

Famed for its easy and quick programming, WorkNC delivers considerable time savings compared to many other CAM systems.

The new graphic user interface features a single, optimized graphics environment and improved ergonomics allowing toolpaths to be programmed even faster than before.

1- The new, easy-to-use WorkNC user interface

The large customizable graphics area is bordered by a tree structure and contemporarily styled icons and toolbars. With the single interface, geometric elements, positions and toolpaths can all be ergonomically selected directly from the screen, allowing the user to gather information quickly and accurately for subsequent tasks and operations.


New graphic user interface : Features a single, optimized graphics environment and improved ergonomics allowing toolpaths to be programmed even faster than before ...
Optimized CAM ergonomy easy to deploy from within a new single graphic user interface ...
Optimized CAM functions : WorkNC G3 is the consolidation and optimization of CAD/CAM functions which have been tried and tested by thousands of WorkNC users worldwide...
An Integrated CAM/CAD environment which brings you the benefits of a new intuitive interface and unified graphic environment ...

2- WorkNC G3 - new & enhanced CAM functions...

G3.V19 includes new fluid cutterpath algorithms which will reduce machining times and improve surface finish. It also has several new toolpaths, including Z Level Finishing with intelligent lead-ins to avoid marking the part and automatic machining of flat areas in High Torque Re-Roughing.

Synplify-Premier-with-Design-Planner- v9.2 for Linux

Synplicity’s Synplify Premier software is the ultimate FPGA timing closure and debug solution. It builds upon Synplicity’s industry-leading synthesis technology by adding graph-based physical synthesis and real-time simulator-like visibility into operating FPGA devices. The Synplify Premier tool’s graph-based physical synthesis technology addresses timing closure by merging optimization, placement, routing and generates a fully placed and physically optimized design ready for final routing using the FPGA vendor routing tool. The highly accurate correlation between the Synplify Premier product’s timing estimates and final design timing enables more aggressive optimization resulting in improved device performance. In addition, the Synplify Premier product offers FPGA Designers and ASIC Prototypers the most efficient method of in-system verification of FPGAs. The Synplify Premier software dramatically accelerates the debug process and provides a rapid and incremental method for finding elusive design problems.

Graph-Based Physical Synthesis
Invented by Synplicity, graph-based physical synthesis improves timing closure by means of a single-pass physical synthesis flow for 90nm FPGAs. Unlike ASICs, proximity does not imply better timing in FPGAs. In graph-based physical synthesis, pre-existing wires, switches, and placement sites used for routing an FPGA can be represented as a detailed routing resource graph. The notion of distance then changes to a measure of delay and availability of wires. The Synplify Premier solution's graph-based physical synthesis technology merges optimization, placement, and routing to generate a fully placed and physically optimized netlist, providing rapid timing closure and a 5 - 20% timing improvement
Simulator-Like Visibility Into a Live FPGA
The Synplify Premier solution quickly finds functional errors in FPGA designs by providing simulator-like visibility into operating FPGA hardware. Based upon technology from the Identify® product, the Synplify Premier tool has integrated debugging software that allows designers to annotate signals and conditions they want to monitor directly in their RTL code. Once the FPGA has been programmed, the RTL debugger is run, allowing users to view actual signal values from a running FPGA directly in their RTL code and debug it, in-system, and at the target operating speed. Advanced triggering helps pinpoint design problems

With the addition of graph-based physical and source-level, in-circuit debugging to the world's best FPGA synthesis technology, the Synplify Premier product is the industry's most comprehensive and productive FPGA design solution.

ASIC Verification
For FPGA users that are prototyping an ASIC, Synplify Premier accepts inputs that are compatible with industry-leading ASIC synthesis tools, allowing you to quickly retarget your FPGA prototype design to an ASIC. Compatibility features includes support for basic Designware components, automatic gated clock conversion, and the use of SDC constraints.

Tanner.EDA. v13

What's New in V13.0
Give your designers a seamless, efficient path from design capture through verification. Tanner EDA tools for analog and mixed-signal IC design enable faster time to market, lower costs, fewer risks, and shorter design cycles. You can implement a complete, integrated design flow with Tanner EDA's HiPer Silicon.

HiPer Silicon is a complete IC design suite that encompasses schematic capture, circuit simulation, waveform probing, physical layout, foundry-compatible DRC, and verification. It can increase your productivity and speed your design from concept to silicon. HiPer Silicon includes S-Edit, T-Spice, L-Edit, and HiPer Verify. Each tool has been significantly enhanced in the past year.

S-Edit
S-Edit enables schematic capture for the most complex full custom IC design. This easy-to-use Windows®-based design environment for schematic capture integrates tightly with Tanner EDA's simulation, physical layout, and verification tools.

New features in S-Edit include:

Hierarchical Find
Search for nets, instances, and objects through the hierarchy with filtering and optionally replace or modify them.
Design Navigator
Efficiently traverse design hierarchy with top-down and bottom-up hierarchical view.
Drag and drop instances directly from the library browser to speed through your design.
Verilog Import
Structural Verilog can be imported into S-Edit as a netlist.
T-Spice
T-Spice lets engineers simulate key blocks during the design process. It puts you in control of simulation jobs with an easy-to-use graphical interface and a faster, more intuitive design environment. T-Spice delivers highly accurate results by supporting the latest foundry, transistor, and behavioral models, with its new multithreading capability for faster runtimes, you will speed your design from concept to silicon faster than ever.

T-Spice includes the following new features:

Verilog-A Support
The Verilog-A feature of T-Spice allows designers to describe and simulate analog circuits behaviorally. For analog designers, Verilog-A enables a top-down approach to circuit design, and allows co-simulation between behavioral blocks and device level analog SPICE netlists. For process developers especially TFT and MEMS process, Verilog-A provides an efficient language for describing device behavior, which is portable across simulators.
T-Spice is compliant with all Verilog-A specifications in the latest standard Verilog-AMS LRM (Language Reference Manual) version 2.2, passes the Compact Model Council test suite, and is fully compatible with Spectre®, H-Spice®, and SmartSpice®.
User Interface Improvements
Simulations now operate on the active Spice file. Filenames of output files are auto-generated from the input filename, and can be optionally placed in a new folder with a time stamped name each time the simulation is run. This allows input files or result files to be easily compared in W-Edit or a 3rd party differencing program.
L-Edit
L-Edit enables analog/mixed-signal designers to automate the layout of similar circuits for different ICs. It meets your needs by combining the fastest rendering available with powerful features. You can get started with minimal training, and draw and edit quickly with fewer keystrokes and mouse clicks than in other layout tools.

Enhanced XrefCells
X-Ref cells, or externally referenced cells, now point directly to the final target cell in a chain of references. This eliminates the need for multiple copies of X-Ref cells that can occur when libraries with multiple reference levels are used.
SDL Enhancements
Flylines are automatically updated when moving instances.
Pins in the SDL Navigator can be viewed by net or by instance.
Existing geometry and geometry that has been added manually can be marked as part of a specific net allowing selection and rip-up of geometry by net.
Structural Verilog can be imported into SDL as a netlist.
Enhanced CurveTools
Wires can have fillets added that retain equal width.
Fillets can be added to curved objects such as a torus and multiple edges are considered as a single edge when adding a fillet/chamfer for curved objects that have been converted to all-angle objects.
Extract Standard
Starting in v13.1, Extract Standard will be much faster but it will still only produce flat netlists. Also, the block (sub-circuit) extract feature of Extract Standard will be discontinued in v13.1 because HiPer Verify now has true hierarchical netlist extraction.
HiPer Verify
HiPer Verify runs Calibre® and Dracula® rule sets hierarchically and natively, and it tightly integrates into the L-Edit environment, allowing design rule violations to be identified and repaired early before they become a major problem.

All-angle hierarchical Calibre compatible netlist extraction
HiPer Verify can extract a hierarchical spice netlist from layout using a Calibre format command file, with performance significantly faster than Tanner Extract Standard. HiPer Verify provides default property computations for built-in devices or user code may be written to compute custom properties from a set of pin and auxiliary layers. User-defined devices (sub-circuits) may also be specified.
HiPer PX
HiPer PX is a 3D physics-based parasitic extraction tool that extracts devices and creates compact and accurate RC models for interconnects up to a user-defined signal frequency. HiPer PX uses a fast and comprehensive interpolation method or an efficient boundary-element method for capacitance extraction and an efficient finite-element method to accurately extract interconnect resistances.

HiPer PX
Extracts 2D interconnect resistance and capacitance for fast extraction times and 3D RC for more accurate parasitic extraction.
Output is a simulation-ready SPICE netlist of devices and RC parasitics.
Supports reduction of RC networks based on a user-specified time constant.

2008.04 0day software

2008-04-29 AUTODESK.AUTOCAD.CIVIL3D.LAND.DESKTOP.COMPANION.V2009
2008-04-28 AUTODESK.AUTOCAD.LAND.DESKTOP.V2009
2008-04-27 INUS.RAPIDFORM.XOR2
2008-04-26 PTC.PROGRESSIVE.DIE.EXTENSION.R5.0.F000
2008-04-25 SIMCON_CADMOULD_3D-F_V2.0
2008-04-24 PTC.PRO.ENGINEER.WILDFIRE.V4.0.M020.WIN32&win64
2008-04-23 DICAD_Strakon_S_v2008_SP1_MULTiLANGUAGE
2008-04-22 SPSS.v16.0.2.Update.Only
2008-04-22 PATHTRACE.EDGECAM.V12.5
2008-04-22 ESI Visual Environment v4.0 Windows
2008-04-20 SIEMENS.NX.I-DEAS.V5M2
2008-04-19 SOFTTECH_STRUDS_V2008
2008-04-19 SIEMENS_EPACTOOL_V3.24
2008-04-15 AUTODESK.AUTOCAD.RASTER.DESIGN.V2009
2008-04-13 AUTODESK.REVIT.ARCHITECTURE.V2009
2008-04-12 AUTODESK.REVIT.STRUCTURE.V2009
2008-04-11 ESI.ProCAST2008 For Windows
2008-04-11 DEFORM 2D V9 SP1
2008-04-10 STFC.DEFORM-3D.V6.1.SP1
2008-04-09 TRIPOS.SYBYL.V8.0.LINUX.IRIX
2008-04-09 DELCAM.ARTCAM.V2008.SP3
2008-04-08 Flowmaster.V7.R1.build.7.5.0
2008-04-08 Bosch.Rexroth.Indraworks.v7.04
2008-04-08 AUTODESK.AUTOCAD.CIVIL.3D.V2009
2008-04-06 EZCAM.EZ-Mill.Turn.v15.0.Cracked
2008-04-06 MoldWorks2008 SP0.1 for SolidWorks
2008-04-05 DELCAM_FEATURECAM_INCL_SOLID_PLUGIN_V14.3
2008-04-05 GibbsCAM.2007.v8.7.13
2008-04-05 ASPENTECH_ASPEN_PIMS_V2006
2008-04-50 ASPENTECH_ASPEN_ORION_V2006
2008-04-05 ASPENTECH_ASPEN_HYSYS_V2006
2008-04-05 ASPENTECH_ASPEN_REFSYS_V2006
2008-04-05 ASPENTECH_ASPEN_ICARUS_V2006
2008-04-05 ASPENTECH_ASPEN_REFSYS_V2006
2008-04-05 ProgeCad_2008_Professional_v8.0.14
2008-04-04 SprutCAM_v4.0.1.30_Expert_Edition
2008-04-03 ALGOR.Designcheck.v21.1.SP1
2008-04-03 Algor.PipePak.v10.2
2008-04-03 ASPENTECH.ASPEN.ENGINEERING.SUITE.V2006
2008-04-03 ASPENTECH.ASPEN.PIMS.FAMILY.V2006
2008-04-03 AUTODESK.QUANTITY.TAKEOFF.V2009
2008-04-02 COADE.CAESAR II V5.0
2008-04-02 Dynasim.Dymola.v7.0
2008-04-02 Sindag.Application.Suite.v2.6
From caxsoft site