Mentor-Graphics-FPGA-Advantage V7.3

FPGA Advantage is a complete Integrated Design Environment (IDE)
targeting high-complexity FPGA device design. The FPGA Advantage IDE
spans the RTL FPGA design flow featuring advanced design entry,
verification, synthesis and implementation sub-flows. FPGA Advantage
accelerates total product design with integration of FPGA IO design
as well as bi-directional integration of the PCB design flow. This
latest release extends the FPGA Advantage IDE to include:
- Improved integration with Precision Synthesis
- Increased "ease of use"
- Extended synthesis device support

Language Independence.
The only unified flow that lets you design for

Any Silicon:
PLD, FPGA, Platform FPGA, Structured ASIC, ASIC Prototypes, ASICs and SOCs
Any Vendor:
Actel, Altera, Atmel, ChipExpress, Lattice, Xilinx, plus any ASIC foundry
Any Language:
VHDL, Verilog, SystemVerilog, C/C++, PSL, SVA

Delivering the technical edge

Maximize QoR, Fmax and area utilization on every leading FPGA platform
Optimize FPGA timing closure with Precision Synthesis and advanced timing analysis
Optimize system timing closure with I/O optimization & PCB integration
Fastest, standards based, multi-lingual simulation platform available

Optimizing your design process

Cut design time in half: Rapid design development process
Practical reuse: RTL reuse methodology
Team productivity: Team design flow and version management
Tune your competitive edge: Flow management and customization
Cut lab time with: FPGA-centric analysis and debug