IAR Embedded Workbench for ARM 5.4

IAR Systems introduced Version 5.40 of IAR Embedded Workbench for ARM. Version 5.40 featurees new debug capabilities for ARM Cortex-M3 processors that were previously only available in dedicated devices and costly debug probes. In addition, Version 5.40 supports source code compliance checking to the MISRA-C:2004 standard, for high integrity applications such as automotive as well as support for the ARM Cortex Microcontroller Software Interface Standard (CMSIS).
News in the current product version Version 5.40 of IAR Embedded Workbench for ARM includes the following new and enhanced functionality:
Information Center A new, web based navigation system that gives easy access to tutorials, product documentation, and example projects. Select Help>Information Center to display the Information Center.
Cortex-R4
Support for code generation and debugging of ARM Cortex-R4 cores.
Cortex-M0

Support for code generation and debugging of ARM Cortex-M0 cores. Debugging on Cortex-M0 hardware is supported using the J-Link probe.
J-Trace for Cortex-M3 Using the J-Trace for Cortex-M3 debug, the debugger can now take advantage of the ETM trace port available on some Cortex-M3 devices. Instruction trace can be started and stopped based on conditions like code locations and data accesses. This feature requires the J-Trace for Cortex-M3 trace probe.
Direct flash erase and download

Flash erase and download can be performed without starting the debugger.
Debugging multiple images C-SPY is now capable of debugging several independently built images during one debug session. Under Project options>Debugger>Images you specify the location of the images to be downloaded in addition to the current application. There is also a new debugger window called Images where you select for which application debug information will be displayed.
Cortex-M3 data breakpoint enhancements
A data breakpoint in Cortex-M3 is now able to break on a specific value in addition to the address of the accessed variable.
Auto refresh in the debugger memory window
The debugger memory window can be refreshed during program execution, both manually and periodically.
Example projects
Over 1400 example projects for various evaluation boards, including evaluation boards from IAR Systems, Actel, Analog Devices, Aiji Systems, ARM, Atmel, Cirrus Logic, Freescale, Keil, LogicPD, Luminary, Micronas, Nohau, OKI, Olimex, Pasat, NXP, Phytec, ST, Texas Instruments and Toshiba are included in the product installation, see the Information Center, or arm\examples directory.
New device support Support for many new devices are added in this release. Please see update-to-date device list for more details.

The compiler optimizer has been tuned to generate industry-leading code size for Cortex-M3 code. The linker can also now compress initialized data to minimize demands on Flash memory: the compressed data will be automatically uncompressed when moved from Flash to RAM by the startup code.