ALDEC-Alint-2009

Design Rule Checking
ALINT™ is an RTL design analysis tool that identifies design issues early in the development cycle. VHDL, Verilog® or mixed-language designs are checked for coding inconsistencies, design structure issues, synthesis, simulation, and clock and reset issues prior to simulation and synthesis. ALINT significantly reduces verification time for complex FPGA and ASIC designs, results in uniform, reusable and reliable code and reduces the risk of costly ASIC re-spins. Comprehensive rule sets are available for VHDL, Verilog and mixed-language designs. ALINT includes powerful utilities for rule management, violation analysis, and debugging.

Top Features

* Fast design analysis of complex ASIC/FPGA-SOC designs
* Comprehensive set of rules to check most complex design issues
* Integrated results analysis and debugging environment
* Supports IEEE VHDL, Verilog and mixed-language designs
* Supports Custom Design Rules
The increasing adoption of large, high-pin-count and high-speed FPGA devices means that right-first-time printed circuit board (PCB) design practices are more essential than ever for ensuring correct system operation. Typically, the PCB design takes place concurrently with the design and programming of the FPGA. Signal and pin assignments are initially made by the FPGA designer, and the board designer must correctly transfer these assignments to the symbols used in their system circuit schematics and board layout. As the board design progresses, pin reassignments may be needed to optimize the PCB layout. These reassignments must in turn be relayed back to the FPGA designer so that the new assignments can be processed through updated placement and routing of the FPGA design. To overcome these challenges, Zuken and Aldec provide an integrated design environment to support these design flows.