Cadence Design Systems, Inc. (NASDAQ: CDNS), the leader in global electronic-design innovation, announced a broad array of new custom IC design capabilities that help chip makers accelerate volume production of large, complex designs, especially at advanced node processes of 65 nanometers and below. These production-proven enhancements to the Virtuoso® suite of technologies further strengthen the holistic approach Cadence® has taken to reduce risk and boost productivity while managing scale and complexity.
Major upgrades to the Cadence Virtuoso custom design platform to be delivered in the latest releases provide tighter manufacturability integration, improved parasitic analysis, along with speedier simulation tools for accurate and efficient verification of complex designs. These new features address the current and emerging challenges faced by semiconductor design companies in the development, physical implementation, verification, and manufacturing of complex chips at advanced process nodes.
In September 2007 Cadence coined the phrase "What you design is what you get," or WYDIWYG, to describe a new approach to advanced-node design that features manufacturing-aware physical implementation and signoff capability that is correlated to foundry signoff. By modeling key manufacturing processes within the implementation flow and optimizing early, overall design time is reduced and designers' confidence is increased that the chip will work as intended.
These latest enhancements further strengthen the WYDIWYG approach, delivering the industry's most comprehensive solutions for custom digital, analog/mixed-signal and system-on-chip designs.
Cadence made the announcement today at CDNLive! EMEA in Munich, Germany, one in a series of global technical conferences for users of Cadence technologies. The newly announced technologies and flows will be demonstrated at the conference, which is sponsored by the Cadence Designer Network. Several leading semiconductor companies will present detailed technical papers today and Wednesday at the CDNLive! conference.
Process variations and circuit parasitics have more impact at advanced nodes, forcing designers to run multi-day simulations to validate their designs for silicon. The Virtuoso Spectre® Circuit Simulator with new turbo technology, available now, targets the toughest analog and mixed-signal designs that have extensive parasitics. It accelerates simulation up to 10 to 20 times, cutting the simulation runs from days to hours. The new version of the simulator also includes parallelization techniques that accelerate simulations even further on popular multi-core hardware platforms. Using these new features, designers can get SPICE accuracy with a streamlined use model, thereby improving design reliability and reducing time to volume production. When these enhancements are used in the Virtuoso Analog Design Environment GXL, parasitic problems can be detected and overcome early in the design flow, rather than later when corrections are much more expensive.
The new IC 6.1.3 release of the Virtuoso custom design platform, the industry's leading solution for analog and mixed-signal design, represents a major upgrade to the technology and is expected to be available in Q308. The new capabilities include enabling concurrent design and manufacturing awareness for yield improvement. Tightly integrated with the Cadence Multi-Mode Simulation technology in the new MMSIM 7.0 release, the upgraded platform provides design centering and yield optimization with boosted performance through Cadence optimization technology (both local and global). New Cadence Express Pcells technology reduces design manipulation by up to 10 times over traditional methods.
Cadence also has integrated space-based routing technology with Virtuoso Layout Suite GXL. This enables custom IC designers to deliver the highest quality of results for their most complex designs.
"With the custom IC technologies announced today, Cadence is delivering a design flow with interwoven manufacturability, and with the performance and interoperability designers need for managing the scale and complexity of their advanced node custom and digital designs," said Jim Miller, executive vice president, Products and Technologies Organization at Cadence. "Cadence is enabling customers working at advanced nodes to produce the highest quality of silicon and maximize yield while meeting aggressive schedule deadlines."
Subscribe to:
Post Comments (Atom)
No comments:
Post a Comment