Synplify-Premier-with-Design-Planner- v9.2 for Linux

Synplicity’s Synplify Premier software is the ultimate FPGA timing closure and debug solution. It builds upon Synplicity’s industry-leading synthesis technology by adding graph-based physical synthesis and real-time simulator-like visibility into operating FPGA devices. The Synplify Premier tool’s graph-based physical synthesis technology addresses timing closure by merging optimization, placement, routing and generates a fully placed and physically optimized design ready for final routing using the FPGA vendor routing tool. The highly accurate correlation between the Synplify Premier product’s timing estimates and final design timing enables more aggressive optimization resulting in improved device performance. In addition, the Synplify Premier product offers FPGA Designers and ASIC Prototypers the most efficient method of in-system verification of FPGAs. The Synplify Premier software dramatically accelerates the debug process and provides a rapid and incremental method for finding elusive design problems.

Graph-Based Physical Synthesis
Invented by Synplicity, graph-based physical synthesis improves timing closure by means of a single-pass physical synthesis flow for 90nm FPGAs. Unlike ASICs, proximity does not imply better timing in FPGAs. In graph-based physical synthesis, pre-existing wires, switches, and placement sites used for routing an FPGA can be represented as a detailed routing resource graph. The notion of distance then changes to a measure of delay and availability of wires. The Synplify Premier solution's graph-based physical synthesis technology merges optimization, placement, and routing to generate a fully placed and physically optimized netlist, providing rapid timing closure and a 5 - 20% timing improvement
Simulator-Like Visibility Into a Live FPGA
The Synplify Premier solution quickly finds functional errors in FPGA designs by providing simulator-like visibility into operating FPGA hardware. Based upon technology from the Identify® product, the Synplify Premier tool has integrated debugging software that allows designers to annotate signals and conditions they want to monitor directly in their RTL code. Once the FPGA has been programmed, the RTL debugger is run, allowing users to view actual signal values from a running FPGA directly in their RTL code and debug it, in-system, and at the target operating speed. Advanced triggering helps pinpoint design problems

With the addition of graph-based physical and source-level, in-circuit debugging to the world's best FPGA synthesis technology, the Synplify Premier product is the industry's most comprehensive and productive FPGA design solution.

ASIC Verification
For FPGA users that are prototyping an ASIC, Synplify Premier accepts inputs that are compatible with industry-leading ASIC synthesis tools, allowing you to quickly retarget your FPGA prototype design to an ASIC. Compatibility features includes support for basic Designware components, automatic gated clock conversion, and the use of SDC constraints.